\doxysection{stm32h7xx\+\_\+ll\+\_\+tim.\+h}
\hypertarget{stm32h7xx__ll__tim_8h_source}{}\label{stm32h7xx__ll__tim_8h_source}\index{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/STM32H7xx\_HAL\_Driver/Inc/stm32h7xx\_ll\_tim.h@{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/STM32H7xx\_HAL\_Driver/Inc/stm32h7xx\_ll\_tim.h}}
\mbox{\hyperlink{stm32h7xx__ll__tim_8h}{Go to the documentation of this file.}}
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\DoxyCodeLine{00561\ \textcolor{comment}{/*\ Exported\ constants\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
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\DoxyCodeLine{00570\ \textcolor{preprocessor}{\#define\ LL\_TIM\_SR\_UIF\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_SR\_UIF\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00571\ \textcolor{preprocessor}{\#define\ LL\_TIM\_SR\_CC1IF\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_SR\_CC1IF\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00572\ \textcolor{preprocessor}{\#define\ LL\_TIM\_SR\_CC2IF\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_SR\_CC2IF\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00573\ \textcolor{preprocessor}{\#define\ LL\_TIM\_SR\_CC3IF\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_SR\_CC3IF\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00574\ \textcolor{preprocessor}{\#define\ LL\_TIM\_SR\_CC4IF\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_SR\_CC4IF\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00575\ \textcolor{preprocessor}{\#define\ LL\_TIM\_SR\_CC5IF\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_SR\_CC5IF\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00576\ \textcolor{preprocessor}{\#define\ LL\_TIM\_SR\_CC6IF\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_SR\_CC6IF\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00577\ \textcolor{preprocessor}{\#define\ LL\_TIM\_SR\_COMIF\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_SR\_COMIF\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00578\ \textcolor{preprocessor}{\#define\ LL\_TIM\_SR\_TIF\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_SR\_TIF\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00579\ \textcolor{preprocessor}{\#define\ LL\_TIM\_SR\_BIF\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_SR\_BIF\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00580\ \textcolor{preprocessor}{\#define\ LL\_TIM\_SR\_B2IF\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_SR\_B2IF\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00581\ \textcolor{preprocessor}{\#define\ LL\_TIM\_SR\_CC1OF\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_SR\_CC1OF\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00582\ \textcolor{preprocessor}{\#define\ LL\_TIM\_SR\_CC2OF\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_SR\_CC2OF\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00583\ \textcolor{preprocessor}{\#define\ LL\_TIM\_SR\_CC3OF\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_SR\_CC3OF\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00584\ \textcolor{preprocessor}{\#define\ LL\_TIM\_SR\_CC4OF\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_SR\_CC4OF\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00585\ \textcolor{preprocessor}{\#define\ LL\_TIM\_SR\_SBIF\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_SR\_SBIF\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
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\DoxyCodeLine{00590\ \textcolor{preprocessor}{\#if\ defined(USE\_FULL\_LL\_DRIVER)}\textcolor{preprocessor}{}}
\DoxyCodeLine{00594\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK\_DISABLE\ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00595\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK\_ENABLE\ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_BDTR\_BKE\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
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\DoxyCodeLine{00603\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK2\_DISABLE\ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00604\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK2\_ENABLE\ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_BDTR\_BK2E\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
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\DoxyCodeLine{00612\ \textcolor{preprocessor}{\#define\ LL\_TIM\_AUTOMATICOUTPUT\_DISABLE\ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00613\ \textcolor{preprocessor}{\#define\ LL\_TIM\_AUTOMATICOUTPUT\_ENABLE\ \ \ \ \ \ \ \ \ \ TIM\_BDTR\_AOE\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
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\DoxyCodeLine{00623\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DIER\_UIE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_DIER\_UIE\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00624\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DIER\_CC1IE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_DIER\_CC1IE\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00625\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DIER\_CC2IE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_DIER\_CC2IE\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00626\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DIER\_CC3IE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_DIER\_CC3IE\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00627\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DIER\_CC4IE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_DIER\_CC4IE\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00628\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DIER\_COMIE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_DIER\_COMIE\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00629\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DIER\_TIE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_DIER\_TIE\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00630\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DIER\_BIE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_DIER\_BIE\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
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\DoxyCodeLine{00638\ \textcolor{preprocessor}{\#define\ LL\_TIM\_UPDATESOURCE\_REGULAR\ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00639\ \textcolor{preprocessor}{\#define\ LL\_TIM\_UPDATESOURCE\_COUNTER\ \ \ \ \ \ \ \ \ \ \ \ TIM\_CR1\_URS\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
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\DoxyCodeLine{00647\ \textcolor{preprocessor}{\#define\ LL\_TIM\_ONEPULSEMODE\_SINGLE\ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_CR1\_OPM\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00648\ \textcolor{preprocessor}{\#define\ LL\_TIM\_ONEPULSEMODE\_REPETITIVE\ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
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\DoxyCodeLine{00656\ \textcolor{preprocessor}{\#define\ LL\_TIM\_COUNTERMODE\_UP\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00657\ \textcolor{preprocessor}{\#define\ LL\_TIM\_COUNTERMODE\_DOWN\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_CR1\_DIR\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00658\ \textcolor{preprocessor}{\#define\ LL\_TIM\_COUNTERMODE\_CENTER\_DOWN\ \ \ \ \ \ \ \ \ TIM\_CR1\_CMS\_0\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00659\ \textcolor{preprocessor}{\#define\ LL\_TIM\_COUNTERMODE\_CENTER\_UP\ \ \ \ \ \ \ \ \ \ \ TIM\_CR1\_CMS\_1\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00660\ \textcolor{preprocessor}{\#define\ LL\_TIM\_COUNTERMODE\_CENTER\_UP\_DOWN\ \ \ \ \ \ TIM\_CR1\_CMS\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
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\DoxyCodeLine{00668\ \textcolor{preprocessor}{\#define\ LL\_TIM\_CLOCKDIVISION\_DIV1\ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00669\ \textcolor{preprocessor}{\#define\ LL\_TIM\_CLOCKDIVISION\_DIV2\ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_CR1\_CKD\_0\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00670\ \textcolor{preprocessor}{\#define\ LL\_TIM\_CLOCKDIVISION\_DIV4\ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_CR1\_CKD\_1\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
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\DoxyCodeLine{00678\ \textcolor{preprocessor}{\#define\ LL\_TIM\_COUNTERDIRECTION\_UP\ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00679\ \textcolor{preprocessor}{\#define\ LL\_TIM\_COUNTERDIRECTION\_DOWN\ \ \ \ \ \ \ \ \ \ \ TIM\_CR1\_DIR\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
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\DoxyCodeLine{00687\ \textcolor{preprocessor}{\#define\ LL\_TIM\_CCUPDATESOURCE\_COMG\_ONLY\ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00688\ \textcolor{preprocessor}{\#define\ LL\_TIM\_CCUPDATESOURCE\_COMG\_AND\_TRGI\ \ \ \ TIM\_CR2\_CCUS\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
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\DoxyCodeLine{00696\ \textcolor{preprocessor}{\#define\ LL\_TIM\_CCDMAREQUEST\_CC\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00697\ \textcolor{preprocessor}{\#define\ LL\_TIM\_CCDMAREQUEST\_UPDATE\ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_CR2\_CCDS\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
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\DoxyCodeLine{00706\ \textcolor{preprocessor}{\#define\ LL\_TIM\_LOCKLEVEL\_1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_BDTR\_LOCK\_0\ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00707\ \textcolor{preprocessor}{\#define\ LL\_TIM\_LOCKLEVEL\_2\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_BDTR\_LOCK\_1\ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00717\ \textcolor{preprocessor}{\#define\ LL\_TIM\_CHANNEL\_CH1N\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_CCER\_CC1NE\ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00719\ \textcolor{preprocessor}{\#define\ LL\_TIM\_CHANNEL\_CH2N\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_CCER\_CC2NE\ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00720\ \textcolor{preprocessor}{\#define\ LL\_TIM\_CHANNEL\_CH3\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_CCER\_CC3E\ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00721\ \textcolor{preprocessor}{\#define\ LL\_TIM\_CHANNEL\_CH3N\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_CCER\_CC3NE\ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00724\ \textcolor{preprocessor}{\#define\ LL\_TIM\_CHANNEL\_CH6\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_CCER\_CC6E\ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
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\DoxyCodeLine{00734\ \textcolor{preprocessor}{\#define\ LL\_TIM\_OCSTATE\_ENABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_CCER\_CC1E\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
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\DoxyCodeLine{00743\ \textcolor{preprocessor}{\#define\ LL\_TIM\_OCMODE\_ASSYMETRIC\_PWM1\ LL\_TIM\_OCMODE\_ASYMMETRIC\_PWM1}}
\DoxyCodeLine{00744\ \textcolor{preprocessor}{\#define\ LL\_TIM\_OCMODE\_ASSYMETRIC\_PWM2\ LL\_TIM\_OCMODE\_ASYMMETRIC\_PWM2}\textcolor{preprocessor}{}}
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\DoxyCodeLine{00752\ \textcolor{preprocessor}{\#define\ LL\_TIM\_OCMODE\_FROZEN\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00753\ \textcolor{preprocessor}{\#define\ LL\_TIM\_OCMODE\_ACTIVE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_CCMR1\_OC1M\_0\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00754\ \textcolor{preprocessor}{\#define\ LL\_TIM\_OCMODE\_INACTIVE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_CCMR1\_OC1M\_1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00755\ \textcolor{preprocessor}{\#define\ LL\_TIM\_OCMODE\_TOGGLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_CCMR1\_OC1M\_1\ |\ TIM\_CCMR1\_OC1M\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00756\ \textcolor{preprocessor}{\#define\ LL\_TIM\_OCMODE\_FORCED\_INACTIVE\ \ \ \ \ \ \ \ \ \ TIM\_CCMR1\_OC1M\_2\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00757\ \textcolor{preprocessor}{\#define\ LL\_TIM\_OCMODE\_FORCED\_ACTIVE\ \ \ \ \ \ \ \ \ \ \ \ (TIM\_CCMR1\_OC1M\_2\ |\ TIM\_CCMR1\_OC1M\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00758\ \textcolor{preprocessor}{\#define\ LL\_TIM\_OCMODE\_PWM1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_CCMR1\_OC1M\_2\ |\ TIM\_CCMR1\_OC1M\_1)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00759\ \textcolor{preprocessor}{\#define\ LL\_TIM\_OCMODE\_PWM2\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_CCMR1\_OC1M\_2\ |\ TIM\_CCMR1\_OC1M\_1\ |\ TIM\_CCMR1\_OC1M\_0)\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00760\ \textcolor{preprocessor}{\#define\ LL\_TIM\_OCMODE\_RETRIG\_OPM1\ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_CCMR1\_OC1M\_3\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00761\ \textcolor{preprocessor}{\#define\ LL\_TIM\_OCMODE\_RETRIG\_OPM2\ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_CCMR1\_OC1M\_3\ |\ TIM\_CCMR1\_OC1M\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00762\ \textcolor{preprocessor}{\#define\ LL\_TIM\_OCMODE\_COMBINED\_PWM1\ \ \ \ \ \ \ \ \ \ \ \ (TIM\_CCMR1\_OC1M\_3\ |\ TIM\_CCMR1\_OC1M\_2)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00763\ \textcolor{preprocessor}{\#define\ LL\_TIM\_OCMODE\_COMBINED\_PWM2\ \ \ \ \ \ \ \ \ \ \ \ (TIM\_CCMR1\_OC1M\_3\ |\ TIM\_CCMR1\_OC1M\_0\ |\ TIM\_CCMR1\_OC1M\_2)\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00764\ \textcolor{preprocessor}{\#define\ LL\_TIM\_OCMODE\_ASYMMETRIC\_PWM1\ \ \ \ \ \ \ \ \ \ (TIM\_CCMR1\_OC1M\_3\ |\ TIM\_CCMR1\_OC1M\_1\ |\ TIM\_CCMR1\_OC1M\_2)\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00765\ \textcolor{preprocessor}{\#define\ LL\_TIM\_OCMODE\_ASYMMETRIC\_PWM2\ \ \ \ \ \ \ \ \ \ (TIM\_CCMR1\_OC1M\_3\ |\ TIM\_CCMR1\_OC1M)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
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\DoxyCodeLine{00773\ \textcolor{preprocessor}{\#define\ LL\_TIM\_OCPOLARITY\_HIGH\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00774\ \textcolor{preprocessor}{\#define\ LL\_TIM\_OCPOLARITY\_LOW\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_CCER\_CC1P\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
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\DoxyCodeLine{00782\ \textcolor{preprocessor}{\#define\ LL\_TIM\_OCIDLESTATE\_LOW\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00783\ \textcolor{preprocessor}{\#define\ LL\_TIM\_OCIDLESTATE\_HIGH\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_CR2\_OIS1\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
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\DoxyCodeLine{00792\ \textcolor{preprocessor}{\#define\ LL\_TIM\_GROUPCH5\_OC1REFC\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_CCR5\_GC5C1\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00793\ \textcolor{preprocessor}{\#define\ LL\_TIM\_GROUPCH5\_OC2REFC\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_CCR5\_GC5C2\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00794\ \textcolor{preprocessor}{\#define\ LL\_TIM\_GROUPCH5\_OC3REFC\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_CCR5\_GC5C3\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
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\DoxyCodeLine{00802\ \textcolor{preprocessor}{\#define\ LL\_TIM\_ACTIVEINPUT\_DIRECTTI\ \ \ \ \ \ \ \ \ \ \ \ (TIM\_CCMR1\_CC1S\_0\ <<\ 16U)\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00803\ \textcolor{preprocessor}{\#define\ LL\_TIM\_ACTIVEINPUT\_INDIRECTTI\ \ \ \ \ \ \ \ \ \ (TIM\_CCMR1\_CC1S\_1\ <<\ 16U)\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00804\ \textcolor{preprocessor}{\#define\ LL\_TIM\_ACTIVEINPUT\_TRC\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_CCMR1\_CC1S\ <<\ 16U)\ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
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\DoxyCodeLine{00812\ \textcolor{preprocessor}{\#define\ LL\_TIM\_ICPSC\_DIV1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00813\ \textcolor{preprocessor}{\#define\ LL\_TIM\_ICPSC\_DIV2\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_CCMR1\_IC1PSC\_0\ <<\ 16U)\ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00814\ \textcolor{preprocessor}{\#define\ LL\_TIM\_ICPSC\_DIV4\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_CCMR1\_IC1PSC\_1\ <<\ 16U)\ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00815\ \textcolor{preprocessor}{\#define\ LL\_TIM\_ICPSC\_DIV8\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_CCMR1\_IC1PSC\ <<\ 16U)\ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{00819\ }
\DoxyCodeLine{00823\ \textcolor{preprocessor}{\#define\ LL\_TIM\_IC\_FILTER\_FDIV1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00824\ \textcolor{preprocessor}{\#define\ LL\_TIM\_IC\_FILTER\_FDIV1\_N2\ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_CCMR1\_IC1F\_0\ <<\ 16U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00825\ \textcolor{preprocessor}{\#define\ LL\_TIM\_IC\_FILTER\_FDIV1\_N4\ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_CCMR1\_IC1F\_1\ <<\ 16U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00826\ \textcolor{preprocessor}{\#define\ LL\_TIM\_IC\_FILTER\_FDIV1\_N8\ \ \ \ \ \ \ \ \ \ \ \ \ \ ((TIM\_CCMR1\_IC1F\_1\ |\ TIM\_CCMR1\_IC1F\_0)\ <<\ 16U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00827\ \textcolor{preprocessor}{\#define\ LL\_TIM\_IC\_FILTER\_FDIV2\_N6\ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_CCMR1\_IC1F\_2\ <<\ 16U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00828\ \textcolor{preprocessor}{\#define\ LL\_TIM\_IC\_FILTER\_FDIV2\_N8\ \ \ \ \ \ \ \ \ \ \ \ \ \ ((TIM\_CCMR1\_IC1F\_2\ |\ TIM\_CCMR1\_IC1F\_0)\ <<\ 16U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00829\ \textcolor{preprocessor}{\#define\ LL\_TIM\_IC\_FILTER\_FDIV4\_N6\ \ \ \ \ \ \ \ \ \ \ \ \ \ ((TIM\_CCMR1\_IC1F\_2\ |\ TIM\_CCMR1\_IC1F\_1)\ <<\ 16U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00830\ \textcolor{preprocessor}{\#define\ LL\_TIM\_IC\_FILTER\_FDIV4\_N8\ \ \ \ \ \ \ \ \ \ \ \ \ \ ((TIM\_CCMR1\_IC1F\_2\ |\ TIM\_CCMR1\_IC1F\_1\ |\ TIM\_CCMR1\_IC1F\_0)\ <<\ 16U)\ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00831\ \textcolor{preprocessor}{\#define\ LL\_TIM\_IC\_FILTER\_FDIV8\_N6\ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_CCMR1\_IC1F\_3\ <<\ 16U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00832\ \textcolor{preprocessor}{\#define\ LL\_TIM\_IC\_FILTER\_FDIV8\_N8\ \ \ \ \ \ \ \ \ \ \ \ \ \ ((TIM\_CCMR1\_IC1F\_3\ |\ TIM\_CCMR1\_IC1F\_0)\ <<\ 16U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00833\ \textcolor{preprocessor}{\#define\ LL\_TIM\_IC\_FILTER\_FDIV16\_N5\ \ \ \ \ \ \ \ \ \ \ \ \ ((TIM\_CCMR1\_IC1F\_3\ |\ TIM\_CCMR1\_IC1F\_1)\ <<\ 16U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00834\ \textcolor{preprocessor}{\#define\ LL\_TIM\_IC\_FILTER\_FDIV16\_N6\ \ \ \ \ \ \ \ \ \ \ \ \ ((TIM\_CCMR1\_IC1F\_3\ |\ TIM\_CCMR1\_IC1F\_1\ |\ TIM\_CCMR1\_IC1F\_0)\ <<\ 16U)\ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00835\ \textcolor{preprocessor}{\#define\ LL\_TIM\_IC\_FILTER\_FDIV16\_N8\ \ \ \ \ \ \ \ \ \ \ \ \ ((TIM\_CCMR1\_IC1F\_3\ |\ TIM\_CCMR1\_IC1F\_2)\ <<\ 16U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00836\ \textcolor{preprocessor}{\#define\ LL\_TIM\_IC\_FILTER\_FDIV32\_N5\ \ \ \ \ \ \ \ \ \ \ \ \ ((TIM\_CCMR1\_IC1F\_3\ |\ TIM\_CCMR1\_IC1F\_2\ |\ TIM\_CCMR1\_IC1F\_0)\ <<\ 16U)\ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00837\ \textcolor{preprocessor}{\#define\ LL\_TIM\_IC\_FILTER\_FDIV32\_N6\ \ \ \ \ \ \ \ \ \ \ \ \ ((TIM\_CCMR1\_IC1F\_3\ |\ TIM\_CCMR1\_IC1F\_2\ |\ TIM\_CCMR1\_IC1F\_1)\ <<\ 16U)\ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00838\ \textcolor{preprocessor}{\#define\ LL\_TIM\_IC\_FILTER\_FDIV32\_N8\ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_CCMR1\_IC1F\ <<\ 16U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{00842\ }
\DoxyCodeLine{00846\ \textcolor{preprocessor}{\#define\ LL\_TIM\_IC\_POLARITY\_RISING\ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00847\ \textcolor{preprocessor}{\#define\ LL\_TIM\_IC\_POLARITY\_FALLING\ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_CCER\_CC1P\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00848\ \textcolor{preprocessor}{\#define\ LL\_TIM\_IC\_POLARITY\_BOTHEDGE\ \ \ \ \ \ \ \ \ \ \ \ (TIM\_CCER\_CC1P\ |\ TIM\_CCER\_CC1NP)\ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{00852\ }
\DoxyCodeLine{00856\ \textcolor{preprocessor}{\#define\ LL\_TIM\_CLOCKSOURCE\_INTERNAL\ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00857\ \textcolor{preprocessor}{\#define\ LL\_TIM\_CLOCKSOURCE\_EXT\_MODE1\ \ \ \ \ \ \ \ \ \ \ (TIM\_SMCR\_SMS\_2\ |\ TIM\_SMCR\_SMS\_1\ |\ TIM\_SMCR\_SMS\_0)\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00858\ \textcolor{preprocessor}{\#define\ LL\_TIM\_CLOCKSOURCE\_EXT\_MODE2\ \ \ \ \ \ \ \ \ \ \ TIM\_SMCR\_ECE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{00862\ }
\DoxyCodeLine{00866\ \textcolor{preprocessor}{\#define\ LL\_TIM\_ENCODERMODE\_X2\_TI1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_SMCR\_SMS\_0\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00867\ \textcolor{preprocessor}{\#define\ LL\_TIM\_ENCODERMODE\_X2\_TI2\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_SMCR\_SMS\_1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00868\ \textcolor{preprocessor}{\#define\ LL\_TIM\_ENCODERMODE\_X4\_TI12\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_SMCR\_SMS\_1\ |\ TIM\_SMCR\_SMS\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{00872\ }
\DoxyCodeLine{00876\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TRGO\_RESET\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00877\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TRGO\_ENABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_CR2\_MMS\_0\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00878\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TRGO\_UPDATE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_CR2\_MMS\_1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00879\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TRGO\_CC1IF\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_CR2\_MMS\_1\ |\ TIM\_CR2\_MMS\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00880\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TRGO\_OC1REF\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_CR2\_MMS\_2\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00881\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TRGO\_OC2REF\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_CR2\_MMS\_2\ |\ TIM\_CR2\_MMS\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00882\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TRGO\_OC3REF\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_CR2\_MMS\_2\ |\ TIM\_CR2\_MMS\_1)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00883\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TRGO\_OC4REF\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_CR2\_MMS\_2\ |\ TIM\_CR2\_MMS\_1\ |\ TIM\_CR2\_MMS\_0)\ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{00887\ }
\DoxyCodeLine{00891\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TRGO2\_RESET\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00892\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TRGO2\_ENABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_CR2\_MMS2\_0\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00893\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TRGO2\_UPDATE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_CR2\_MMS2\_1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00894\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TRGO2\_CC1F\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_CR2\_MMS2\_1\ |\ TIM\_CR2\_MMS2\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00895\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TRGO2\_OC1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_CR2\_MMS2\_2\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00896\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TRGO2\_OC2\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_CR2\_MMS2\_2\ |\ TIM\_CR2\_MMS2\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00897\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TRGO2\_OC3\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_CR2\_MMS2\_2\ |\ TIM\_CR2\_MMS2\_1)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00898\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TRGO2\_OC4\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_CR2\_MMS2\_2\ |\ TIM\_CR2\_MMS2\_1\ |\ TIM\_CR2\_MMS2\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00899\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TRGO2\_OC5\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_CR2\_MMS2\_3\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00900\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TRGO2\_OC6\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_CR2\_MMS2\_3\ |\ TIM\_CR2\_MMS2\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00901\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TRGO2\_OC4\_RISINGFALLING\ \ \ \ \ \ \ \ \ (TIM\_CR2\_MMS2\_3\ |\ TIM\_CR2\_MMS2\_1)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00902\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TRGO2\_OC6\_RISINGFALLING\ \ \ \ \ \ \ \ \ (TIM\_CR2\_MMS2\_3\ |\ TIM\_CR2\_MMS2\_1\ |\ TIM\_CR2\_MMS2\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00903\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TRGO2\_OC4\_RISING\_OC6\_RISING\ \ \ \ \ (TIM\_CR2\_MMS2\_3\ |\ TIM\_CR2\_MMS2\_2)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00904\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TRGO2\_OC4\_RISING\_OC6\_FALLING\ \ \ \ (TIM\_CR2\_MMS2\_3\ |\ TIM\_CR2\_MMS2\_2\ |\ TIM\_CR2\_MMS2\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00905\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TRGO2\_OC5\_RISING\_OC6\_RISING\ \ \ \ \ (TIM\_CR2\_MMS2\_3\ |\ TIM\_CR2\_MMS2\_2\ |TIM\_CR2\_MMS2\_1)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00906\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TRGO2\_OC5\_RISING\_OC6\_FALLING\ \ \ \ (TIM\_CR2\_MMS2\_3\ |\ TIM\_CR2\_MMS2\_2\ |\ TIM\_CR2\_MMS2\_1\ |\ TIM\_CR2\_MMS2\_0)\ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{00910\ }
\DoxyCodeLine{00914\ \textcolor{preprocessor}{\#define\ LL\_TIM\_SLAVEMODE\_DISABLED\ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00915\ \textcolor{preprocessor}{\#define\ LL\_TIM\_SLAVEMODE\_RESET\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_SMCR\_SMS\_2\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00916\ \textcolor{preprocessor}{\#define\ LL\_TIM\_SLAVEMODE\_GATED\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_SMCR\_SMS\_2\ |\ TIM\_SMCR\_SMS\_0)\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00917\ \textcolor{preprocessor}{\#define\ LL\_TIM\_SLAVEMODE\_TRIGGER\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_SMCR\_SMS\_2\ |\ TIM\_SMCR\_SMS\_1)\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00918\ \textcolor{preprocessor}{\#define\ LL\_TIM\_SLAVEMODE\_COMBINED\_RESETTRIGGER\ TIM\_SMCR\_SMS\_3\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{00922\ }
\DoxyCodeLine{00926\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TS\_ITR0\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00927\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TS\_ITR1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_SMCR\_TS\_0\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00928\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TS\_ITR2\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_SMCR\_TS\_1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00929\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TS\_ITR3\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_SMCR\_TS\_0\ |\ TIM\_SMCR\_TS\_1)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00930\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TS\_ITR4\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_SMCR\_TS\_3)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00931\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TS\_ITR5\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_SMCR\_TS\_0\ |\ TIM\_SMCR\_TS\_3)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00932\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TS\_ITR6\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_SMCR\_TS\_1\ |\ TIM\_SMCR\_TS\_3)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00933\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TS\_ITR7\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_SMCR\_TS\_0\ |\ TIM\_SMCR\_TS\_1\ |\ TIM\_SMCR\_TS\_3)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00934\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TS\_ITR8\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_SMCR\_TS\_2\ |\ TIM\_SMCR\_TS\_3)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00935\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TS\_ITR9\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_SMCR\_TS\_0\ |\ TIM\_SMCR\_TS\_2\ |\ TIM\_SMCR\_TS\_3)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00936\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TS\_ITR10\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_SMCR\_TS\_1\ |\ TIM\_SMCR\_TS\_2\ |\ TIM\_SMCR\_TS\_3)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00937\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TS\_ITR11\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_SMCR\_TS\_0\ |\ TIM\_SMCR\_TS\_1\ |\ TIM\_SMCR\_TS\_2\ |\ TIM\_SMCR\_TS\_3)\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00938\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TS\_ITR12\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_SMCR\_TS\_4)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00939\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TS\_ITR13\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_SMCR\_TS\_0\ |\ TIM\_SMCR\_TS\_4)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00940\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TS\_TI1F\_ED\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_SMCR\_TS\_2\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00941\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TS\_TI1FP1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_SMCR\_TS\_2\ |\ TIM\_SMCR\_TS\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00942\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TS\_TI2FP2\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_SMCR\_TS\_2\ |\ TIM\_SMCR\_TS\_1)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00943\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TS\_ETRF\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_SMCR\_TS\_2\ |\ TIM\_SMCR\_TS\_1\ |\ TIM\_SMCR\_TS\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{00947\ }
\DoxyCodeLine{00951\ \textcolor{preprocessor}{\#define\ LL\_TIM\_ETR\_POLARITY\_NONINVERTED\ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00952\ \textcolor{preprocessor}{\#define\ LL\_TIM\_ETR\_POLARITY\_INVERTED\ \ \ \ \ \ \ \ \ \ \ TIM\_SMCR\_ETP\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{00956\ }
\DoxyCodeLine{00960\ \textcolor{preprocessor}{\#define\ LL\_TIM\_ETR\_PRESCALER\_DIV1\ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00961\ \textcolor{preprocessor}{\#define\ LL\_TIM\_ETR\_PRESCALER\_DIV2\ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_SMCR\_ETPS\_0\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00962\ \textcolor{preprocessor}{\#define\ LL\_TIM\_ETR\_PRESCALER\_DIV4\ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_SMCR\_ETPS\_1\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00963\ \textcolor{preprocessor}{\#define\ LL\_TIM\_ETR\_PRESCALER\_DIV8\ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_SMCR\_ETPS\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{00967\ }
\DoxyCodeLine{00971\ \textcolor{preprocessor}{\#define\ LL\_TIM\_ETR\_FILTER\_FDIV1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00972\ \textcolor{preprocessor}{\#define\ LL\_TIM\_ETR\_FILTER\_FDIV1\_N2\ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_SMCR\_ETF\_0\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00973\ \textcolor{preprocessor}{\#define\ LL\_TIM\_ETR\_FILTER\_FDIV1\_N4\ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_SMCR\_ETF\_1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00974\ \textcolor{preprocessor}{\#define\ LL\_TIM\_ETR\_FILTER\_FDIV1\_N8\ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_SMCR\_ETF\_1\ |\ TIM\_SMCR\_ETF\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00975\ \textcolor{preprocessor}{\#define\ LL\_TIM\_ETR\_FILTER\_FDIV2\_N6\ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_SMCR\_ETF\_2\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00976\ \textcolor{preprocessor}{\#define\ LL\_TIM\_ETR\_FILTER\_FDIV2\_N8\ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_SMCR\_ETF\_2\ |\ TIM\_SMCR\_ETF\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00977\ \textcolor{preprocessor}{\#define\ LL\_TIM\_ETR\_FILTER\_FDIV4\_N6\ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_SMCR\_ETF\_2\ |\ TIM\_SMCR\_ETF\_1)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00978\ \textcolor{preprocessor}{\#define\ LL\_TIM\_ETR\_FILTER\_FDIV4\_N8\ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_SMCR\_ETF\_2\ |\ TIM\_SMCR\_ETF\_1\ |\ TIM\_SMCR\_ETF\_0)\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00979\ \textcolor{preprocessor}{\#define\ LL\_TIM\_ETR\_FILTER\_FDIV8\_N6\ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_SMCR\_ETF\_3\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00980\ \textcolor{preprocessor}{\#define\ LL\_TIM\_ETR\_FILTER\_FDIV8\_N8\ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_SMCR\_ETF\_3\ |\ TIM\_SMCR\_ETF\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00981\ \textcolor{preprocessor}{\#define\ LL\_TIM\_ETR\_FILTER\_FDIV16\_N5\ \ \ \ \ \ \ \ \ \ \ \ (TIM\_SMCR\_ETF\_3\ |\ TIM\_SMCR\_ETF\_1)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00982\ \textcolor{preprocessor}{\#define\ LL\_TIM\_ETR\_FILTER\_FDIV16\_N6\ \ \ \ \ \ \ \ \ \ \ \ (TIM\_SMCR\_ETF\_3\ |\ TIM\_SMCR\_ETF\_1\ |\ TIM\_SMCR\_ETF\_0)\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00983\ \textcolor{preprocessor}{\#define\ LL\_TIM\_ETR\_FILTER\_FDIV16\_N8\ \ \ \ \ \ \ \ \ \ \ \ (TIM\_SMCR\_ETF\_3\ |\ TIM\_SMCR\_ETF\_2)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00984\ \textcolor{preprocessor}{\#define\ LL\_TIM\_ETR\_FILTER\_FDIV32\_N5\ \ \ \ \ \ \ \ \ \ \ \ (TIM\_SMCR\_ETF\_3\ |\ TIM\_SMCR\_ETF\_2\ |\ TIM\_SMCR\_ETF\_0)\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00985\ \textcolor{preprocessor}{\#define\ LL\_TIM\_ETR\_FILTER\_FDIV32\_N6\ \ \ \ \ \ \ \ \ \ \ \ (TIM\_SMCR\_ETF\_3\ |\ TIM\_SMCR\_ETF\_2\ |\ TIM\_SMCR\_ETF\_1)\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00986\ \textcolor{preprocessor}{\#define\ LL\_TIM\_ETR\_FILTER\_FDIV32\_N8\ \ \ \ \ \ \ \ \ \ \ \ TIM\_SMCR\_ETF\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{00990\ }
\DoxyCodeLine{00991\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM1\_ETRSOURCE\_GPIO\ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00992\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM1\_ETRSOURCE\_COMP1\ \ \ \ \ \ \ TIM1\_AF1\_ETRSEL\_0\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00993\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM1\_ETRSOURCE\_COMP2\ \ \ \ \ \ \ TIM1\_AF1\_ETRSEL\_1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00994\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM1\_ETRSOURCE\_ADC1\_AWD1\ \ \ (TIM1\_AF1\_ETRSEL\_1\ |\ TIM1\_AF1\_ETRSEL\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00995\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM1\_ETRSOURCE\_ADC1\_AWD2\ \ \ (TIM1\_AF1\_ETRSEL\_2)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00996\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM1\_ETRSOURCE\_ADC1\_AWD3\ \ \ (TIM1\_AF1\_ETRSEL\_2\ |\ TIM1\_AF1\_ETRSEL\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00997\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM1\_ETRSOURCE\_ADC3\_AWD1\ \ \ (TIM1\_AF1\_ETRSEL\_2\ |\ TIM1\_AF1\_ETRSEL\_1)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00998\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM1\_ETRSOURCE\_ADC3\_AWD2\ \ \ (TIM1\_AF1\_ETRSEL\_2\ |\ TIM1\_AF1\_ETRSEL\_1\ |\ TIM1\_AF1\_ETRSEL\_0)\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00999\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM1\_ETRSOURCE\_ADC3\_AWD3\ \ \ TIM1\_AF1\_ETRSEL\_3\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01000\ }
\DoxyCodeLine{01001\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM8\_ETRSOURCE\_GPIO\ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01002\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM8\_ETRSOURCE\_COMP1\ \ \ \ \ \ \ TIM8\_AF1\_ETRSEL\_0\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01003\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM8\_ETRSOURCE\_COMP2\ \ \ \ \ \ \ TIM8\_AF1\_ETRSEL\_1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01004\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM8\_ETRSOURCE\_ADC2\_AWD1\ \ \ (TIM8\_AF1\_ETRSEL\_1\ |\ TIM8\_AF1\_ETRSEL\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01005\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM8\_ETRSOURCE\_ADC2\_AWD2\ \ \ (TIM8\_AF1\_ETRSEL\_2)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01006\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM8\_ETRSOURCE\_ADC2\_AWD3\ \ \ (TIM8\_AF1\_ETRSEL\_2\ |\ TIM8\_AF1\_ETRSEL\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01007\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM8\_ETRSOURCE\_ADC3\_AWD1\ \ \ (TIM8\_AF1\_ETRSEL\_2\ |\ TIM8\_AF1\_ETRSEL\_1)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01008\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM8\_ETRSOURCE\_ADC3\_AWD2\ \ \ (TIM8\_AF1\_ETRSEL\_2\ |\ TIM8\_AF1\_ETRSEL\_1\ |\ TIM8\_AF1\_ETRSEL\_0)\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01009\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM8\_ETRSOURCE\_ADC3\_AWD3\ \ \ TIM8\_AF1\_ETRSEL\_3\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01010\ }
\DoxyCodeLine{01011\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM2\_ETRSOURCE\_GPIO\ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01012\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM2\_ETRSOURCE\_COMP1\ \ \ \ \ \ \ (TIM2\_AF1\_ETRSEL\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01013\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM2\_ETRSOURCE\_COMP2\ \ \ \ \ \ \ (TIM2\_AF1\_ETRSEL\_1)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01014\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM2\_ETRSOURCE\_RCC\_LSE\ \ \ \ \ (TIM2\_AF1\_ETRSEL\_1\ |\ TIM8\_AF1\_ETRSEL\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01015\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM2\_ETRSOURCE\_SAI1\_FSA\ \ \ \ TIM2\_AF1\_ETRSEL\_2\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01016\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM2\_ETRSOURCE\_SAI1\_FSB\ \ \ \ (TIM2\_AF1\_ETRSEL\_2\ |\ TIM8\_AF1\_ETRSEL\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01017\ }
\DoxyCodeLine{01018\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM3\_ETRSOURCE\_GPIO\ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01019\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM3\_ETRSOURCE\_COMP1\ \ \ \ \ \ \ TIM3\_AF1\_ETRSEL\_0\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01020\ }
\DoxyCodeLine{01021\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM5\_ETRSOURCE\_GPIO\ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01022\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM5\_ETRSOURCE\_SAI2\_FSA\ \ \ \ TIM5\_AF1\_ETRSEL\_0\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01023\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM5\_ETRSOURCE\_SAI2\_FSB\ \ \ \ TIM5\_AF1\_ETRSEL\_1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01024\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM5\_ETRSOURCE\_SAI4\_FSA\ \ \ \ TIM5\_AF1\_ETRSEL\_0\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01025\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM5\_ETRSOURCE\_SAI4\_FSB\ \ \ \ TIM5\_AF1\_ETRSEL\_1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01026\ }
\DoxyCodeLine{01027\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM23\_ETRSOURCE\_GPIO\ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01028\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM23\_ETRSOURCE\_COMP1\ \ \ \ \ \ (TIM2\_AF1\_ETRSEL\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01029\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM23\_ETRSOURCE\_COMP2\ \ \ \ \ \ (TIM2\_AF1\_ETRSEL\_1)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01030\ }
\DoxyCodeLine{01031\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM24\_ETRSOURCE\_GPIO\ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01032\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM24\_ETRSOURCE\_SAI4\_FSA\ \ \ \ TIM5\_AF1\_ETRSEL\_0\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01033\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM24\_ETRSOURCE\_SAI4\_FSB\ \ \ \ TIM5\_AF1\_ETRSEL\_1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01034\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM24\_ETRSOURCE\_SAI1\_FSA\ \ \ \ (TIM2\_AF1\_ETRSEL\_1\ |\ TIM8\_AF1\_ETRSEL\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01035\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM24\_ETRSOURCE\_SAI1\_FSB\ \ \ \ TIM2\_AF1\_ETRSEL\_2\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01036\ }
\DoxyCodeLine{01040\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK\_POLARITY\_LOW\ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01041\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK\_POLARITY\_HIGH\ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_BDTR\_BKP\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{01045\ }
\DoxyCodeLine{01049\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK\_FILTER\_FDIV1\ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01050\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK\_FILTER\_FDIV1\_N2\ \ \ \ \ \ \ \ \ \ \ 0x00010000U\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01051\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK\_FILTER\_FDIV1\_N4\ \ \ \ \ \ \ \ \ \ \ 0x00020000U\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01052\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK\_FILTER\_FDIV1\_N8\ \ \ \ \ \ \ \ \ \ \ 0x00030000U\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01053\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK\_FILTER\_FDIV2\_N6\ \ \ \ \ \ \ \ \ \ \ 0x00040000U\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01054\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK\_FILTER\_FDIV2\_N8\ \ \ \ \ \ \ \ \ \ \ 0x00050000U\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01055\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK\_FILTER\_FDIV4\_N6\ \ \ \ \ \ \ \ \ \ \ 0x00060000U\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01056\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK\_FILTER\_FDIV4\_N8\ \ \ \ \ \ \ \ \ \ \ 0x00070000U\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01057\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK\_FILTER\_FDIV8\_N6\ \ \ \ \ \ \ \ \ \ \ 0x00080000U\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01058\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK\_FILTER\_FDIV8\_N8\ \ \ \ \ \ \ \ \ \ \ 0x00090000U\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01059\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK\_FILTER\_FDIV16\_N5\ \ \ \ \ \ \ \ \ \ 0x000A0000U\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01060\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK\_FILTER\_FDIV16\_N6\ \ \ \ \ \ \ \ \ \ 0x000B0000U\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01061\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK\_FILTER\_FDIV16\_N8\ \ \ \ \ \ \ \ \ \ 0x000C0000U\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01062\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK\_FILTER\_FDIV32\_N5\ \ \ \ \ \ \ \ \ \ 0x000D0000U\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01063\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK\_FILTER\_FDIV32\_N6\ \ \ \ \ \ \ \ \ \ 0x000E0000U\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01064\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK\_FILTER\_FDIV32\_N8\ \ \ \ \ \ \ \ \ \ 0x000F0000U\ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{01068\ }
\DoxyCodeLine{01072\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK2\_POLARITY\_LOW\ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01073\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK2\_POLARITY\_HIGH\ \ \ \ \ \ \ \ \ \ \ \ TIM\_BDTR\_BK2P\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{01077\ }
\DoxyCodeLine{01081\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK2\_FILTER\_FDIV1\ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01082\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK2\_FILTER\_FDIV1\_N2\ \ \ \ \ \ \ \ \ \ 0x00100000U\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01083\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK2\_FILTER\_FDIV1\_N4\ \ \ \ \ \ \ \ \ \ 0x00200000U\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01084\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK2\_FILTER\_FDIV1\_N8\ \ \ \ \ \ \ \ \ \ 0x00300000U\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01085\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK2\_FILTER\_FDIV2\_N6\ \ \ \ \ \ \ \ \ \ 0x00400000U\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01086\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK2\_FILTER\_FDIV2\_N8\ \ \ \ \ \ \ \ \ \ 0x00500000U\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01087\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK2\_FILTER\_FDIV4\_N6\ \ \ \ \ \ \ \ \ \ 0x00600000U\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01088\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK2\_FILTER\_FDIV4\_N8\ \ \ \ \ \ \ \ \ \ 0x00700000U\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01089\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK2\_FILTER\_FDIV8\_N6\ \ \ \ \ \ \ \ \ \ 0x00800000U\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01090\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK2\_FILTER\_FDIV8\_N8\ \ \ \ \ \ \ \ \ \ 0x00900000U\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01091\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK2\_FILTER\_FDIV16\_N5\ \ \ \ \ \ \ \ \ 0x00A00000U\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01092\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK2\_FILTER\_FDIV16\_N6\ \ \ \ \ \ \ \ \ 0x00B00000U\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01093\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK2\_FILTER\_FDIV16\_N8\ \ \ \ \ \ \ \ \ 0x00C00000U\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01094\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK2\_FILTER\_FDIV32\_N5\ \ \ \ \ \ \ \ \ 0x00D00000U\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01095\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK2\_FILTER\_FDIV32\_N6\ \ \ \ \ \ \ \ \ 0x00E00000U\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01096\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK2\_FILTER\_FDIV32\_N8\ \ \ \ \ \ \ \ \ 0x00F00000U\ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{01100\ }
\DoxyCodeLine{01104\ \textcolor{preprocessor}{\#define\ LL\_TIM\_OSSI\_DISABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01105\ \textcolor{preprocessor}{\#define\ LL\_TIM\_OSSI\_ENABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_BDTR\_OSSI\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{01109\ }
\DoxyCodeLine{01113\ \textcolor{preprocessor}{\#define\ LL\_TIM\_OSSR\_DISABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01114\ \textcolor{preprocessor}{\#define\ LL\_TIM\_OSSR\_ENABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_BDTR\_OSSR\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{01118\ }
\DoxyCodeLine{01119\ \textcolor{preprocessor}{\#if\ \ \ defined(TIM\_BREAK\_INPUT\_SUPPORT)}\textcolor{preprocessor}{}}
\DoxyCodeLine{01123\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK\_INPUT\_BKIN\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01124\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK\_INPUT\_BKIN2\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000004U\ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{01128\ }
\DoxyCodeLine{01132\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BKIN\_SOURCE\_BKIN\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM1\_AF1\_BKINE\ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01133\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BKIN\_SOURCE\_BKCOMP1\ \ \ \ \ \ \ \ \ \ \ \ \ TIM1\_AF1\_BKCMP1E\ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01134\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BKIN\_SOURCE\_BKCOMP2\ \ \ \ \ \ \ \ \ \ \ \ \ TIM1\_AF1\_BKCMP2E\ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01135\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BKIN\_SOURCE\_DF1BK\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM1\_AF1\_BKDF1BK0E\ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{01139\ }
\DoxyCodeLine{01143\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BKIN\_POLARITY\_LOW\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM1\_AF1\_BKINP\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01144\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BKIN\_POLARITY\_HIGH\ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{01148\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ TIM\_BREAK\_INPUT\_SUPPORT\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{01149\ }
\DoxyCodeLine{01150\ \textcolor{preprocessor}{\#if\ defined(TIM\_BDTR\_BKBID)}\textcolor{preprocessor}{}}
\DoxyCodeLine{01154\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK\_AFMODE\_INPUT\ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01155\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK\_AFMODE\_BIDIRECTIONAL\ \ \ \ \ \ TIM\_BDTR\_BKBID\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{01159\ }
\DoxyCodeLine{01163\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK2\_AFMODE\_INPUT\ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01164\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BREAK2\_AFMODE\_BIDIRECTIONAL\ \ \ \ \ TIM\_BDTR\_BK2BID\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{01168\ }
\DoxyCodeLine{01172\ \textcolor{preprocessor}{\#define\ LL\_TIM\_ReArmBRK(\_PARAM\_)}}
\DoxyCodeLine{01173\ \textcolor{preprocessor}{\#define\ LL\_TIM\_ReArmBRK2(\_PARAM\_)}\textcolor{preprocessor}{}}
\DoxyCodeLine{01177\ }
\DoxyCodeLine{01178\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*TIM\_BDTR\_BKBID\ */}\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{01182\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DMABURST\_BASEADDR\_CR1\ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01183\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DMABURST\_BASEADDR\_CR2\ \ \ \ \ \ \ \ \ \ \ TIM\_DCR\_DBA\_0\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01184\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DMABURST\_BASEADDR\_SMCR\ \ \ \ \ \ \ \ \ \ TIM\_DCR\_DBA\_1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01185\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DMABURST\_BASEADDR\_DIER\ \ \ \ \ \ \ \ \ \ (TIM\_DCR\_DBA\_1\ |\ \ TIM\_DCR\_DBA\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01186\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DMABURST\_BASEADDR\_SR\ \ \ \ \ \ \ \ \ \ \ \ TIM\_DCR\_DBA\_2\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01187\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DMABURST\_BASEADDR\_EGR\ \ \ \ \ \ \ \ \ \ \ (TIM\_DCR\_DBA\_2\ |\ TIM\_DCR\_DBA\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01188\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DMABURST\_BASEADDR\_CCMR1\ \ \ \ \ \ \ \ \ (TIM\_DCR\_DBA\_2\ |\ TIM\_DCR\_DBA\_1)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01189\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DMABURST\_BASEADDR\_CCMR2\ \ \ \ \ \ \ \ \ (TIM\_DCR\_DBA\_2\ |\ TIM\_DCR\_DBA\_1\ |\ TIM\_DCR\_DBA\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01190\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DMABURST\_BASEADDR\_CCER\ \ \ \ \ \ \ \ \ \ TIM\_DCR\_DBA\_3\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01191\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DMABURST\_BASEADDR\_CNT\ \ \ \ \ \ \ \ \ \ \ (TIM\_DCR\_DBA\_3\ |\ TIM\_DCR\_DBA\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01192\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DMABURST\_BASEADDR\_PSC\ \ \ \ \ \ \ \ \ \ \ (TIM\_DCR\_DBA\_3\ |\ TIM\_DCR\_DBA\_1)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01193\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DMABURST\_BASEADDR\_ARR\ \ \ \ \ \ \ \ \ \ \ (TIM\_DCR\_DBA\_3\ |\ TIM\_DCR\_DBA\_1\ |\ TIM\_DCR\_DBA\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01194\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DMABURST\_BASEADDR\_RCR\ \ \ \ \ \ \ \ \ \ \ (TIM\_DCR\_DBA\_3\ |\ TIM\_DCR\_DBA\_2)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01195\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DMABURST\_BASEADDR\_CCR1\ \ \ \ \ \ \ \ \ \ (TIM\_DCR\_DBA\_3\ |\ TIM\_DCR\_DBA\_2\ |\ TIM\_DCR\_DBA\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01196\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DMABURST\_BASEADDR\_CCR2\ \ \ \ \ \ \ \ \ \ (TIM\_DCR\_DBA\_3\ |\ TIM\_DCR\_DBA\_2\ |\ TIM\_DCR\_DBA\_1)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01197\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DMABURST\_BASEADDR\_CCR3\ \ \ \ \ \ \ \ \ \ (TIM\_DCR\_DBA\_3\ |\ TIM\_DCR\_DBA\_2\ |\ TIM\_DCR\_DBA\_1\ |\ TIM\_DCR\_DBA\_0)\ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01198\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DMABURST\_BASEADDR\_CCR4\ \ \ \ \ \ \ \ \ \ TIM\_DCR\_DBA\_4\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01199\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DMABURST\_BASEADDR\_BDTR\ \ \ \ \ \ \ \ \ \ (TIM\_DCR\_DBA\_4\ |\ TIM\_DCR\_DBA\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01200\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DMABURST\_BASEADDR\_CCMR3\ \ \ \ \ \ \ \ \ (TIM\_DCR\_DBA\_4\ |\ TIM\_DCR\_DBA\_2\ |\ TIM\_DCR\_DBA\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01201\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DMABURST\_BASEADDR\_CCR5\ \ \ \ \ \ \ \ \ \ (TIM\_DCR\_DBA\_4\ |\ TIM\_DCR\_DBA\_2\ |\ TIM\_DCR\_DBA\_1)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01202\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DMABURST\_BASEADDR\_CCR6\ \ \ \ \ \ \ \ \ \ (TIM\_DCR\_DBA\_4\ |\ TIM\_DCR\_DBA\_2\ |\ TIM\_DCR\_DBA\_1\ |\ TIM\_DCR\_DBA\_0)\ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01203\ \textcolor{preprocessor}{\#if\ defined(TIM1\_AF1\_BKINE)\&\&defined(TIM1\_AF2\_BKINE)}}
\DoxyCodeLine{01204\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DMABURST\_BASEADDR\_AF1\ \ \ \ \ \ \ \ \ \ \ (TIM\_DCR\_DBA\_4\ |\ TIM\_DCR\_DBA\_3)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01205\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DMABURST\_BASEADDR\_AF2\ \ \ \ \ \ \ \ \ \ \ (TIM\_DCR\_DBA\_4\ |\ TIM\_DCR\_DBA\_3\ |\ TIM\_DCR\_DBA\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01206\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ TIM1\_AF1\_BKINE\ \&\&\ TIM1\_AF2\_BKINE\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{01207\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DMABURST\_BASEADDR\_TISEL\ \ \ \ \ \ \ \ \ (TIM\_DCR\_DBA\_4\ |\ TIM\_DCR\_DBA\_3\ |\ TIM\_DCR\_DBA\_1)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{01211\ }
\DoxyCodeLine{01215\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DMABURST\_LENGTH\_1TRANSFER\ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01216\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DMABURST\_LENGTH\_2TRANSFERS\ \ \ \ \ \ TIM\_DCR\_DBL\_0\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01217\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DMABURST\_LENGTH\_3TRANSFERS\ \ \ \ \ \ TIM\_DCR\_DBL\_1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01218\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DMABURST\_LENGTH\_4TRANSFERS\ \ \ \ \ \ (TIM\_DCR\_DBL\_1\ |\ \ TIM\_DCR\_DBL\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01219\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DMABURST\_LENGTH\_5TRANSFERS\ \ \ \ \ \ TIM\_DCR\_DBL\_2\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01220\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DMABURST\_LENGTH\_6TRANSFERS\ \ \ \ \ \ (TIM\_DCR\_DBL\_2\ |\ TIM\_DCR\_DBL\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01221\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DMABURST\_LENGTH\_7TRANSFERS\ \ \ \ \ \ (TIM\_DCR\_DBL\_2\ |\ TIM\_DCR\_DBL\_1)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01222\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DMABURST\_LENGTH\_8TRANSFERS\ \ \ \ \ \ (TIM\_DCR\_DBL\_2\ |\ TIM\_DCR\_DBL\_1\ |\ TIM\_DCR\_DBL\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01223\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DMABURST\_LENGTH\_9TRANSFERS\ \ \ \ \ \ TIM\_DCR\_DBL\_3\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01224\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DMABURST\_LENGTH\_10TRANSFERS\ \ \ \ \ (TIM\_DCR\_DBL\_3\ |\ TIM\_DCR\_DBL\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01225\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DMABURST\_LENGTH\_11TRANSFERS\ \ \ \ \ (TIM\_DCR\_DBL\_3\ |\ TIM\_DCR\_DBL\_1)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01226\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DMABURST\_LENGTH\_12TRANSFERS\ \ \ \ \ (TIM\_DCR\_DBL\_3\ |\ TIM\_DCR\_DBL\_1\ |\ TIM\_DCR\_DBL\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01227\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DMABURST\_LENGTH\_13TRANSFERS\ \ \ \ \ (TIM\_DCR\_DBL\_3\ |\ TIM\_DCR\_DBL\_2)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01228\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DMABURST\_LENGTH\_14TRANSFERS\ \ \ \ \ (TIM\_DCR\_DBL\_3\ |\ TIM\_DCR\_DBL\_2\ |\ TIM\_DCR\_DBL\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01229\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DMABURST\_LENGTH\_15TRANSFERS\ \ \ \ \ (TIM\_DCR\_DBL\_3\ |\ TIM\_DCR\_DBL\_2\ |\ TIM\_DCR\_DBL\_1)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01230\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DMABURST\_LENGTH\_16TRANSFERS\ \ \ \ \ (TIM\_DCR\_DBL\_3\ |\ TIM\_DCR\_DBL\_2\ |\ TIM\_DCR\_DBL\_1\ |\ TIM\_DCR\_DBL\_0)\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01231\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DMABURST\_LENGTH\_17TRANSFERS\ \ \ \ \ TIM\_DCR\_DBL\_4\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01232\ \textcolor{preprocessor}{\#define\ LL\_TIM\_DMABURST\_LENGTH\_18TRANSFERS\ \ \ \ \ (TIM\_DCR\_DBL\_4\ |\ \ TIM\_DCR\_DBL\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{01236\ }
\DoxyCodeLine{01240\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM1\_TI1\_RMP\_GPIO\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01241\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM1\_TI1\_RMP\_COMP1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_TISEL\_TI1SEL\_0\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{01245\ }
\DoxyCodeLine{01249\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM8\_TI1\_RMP\_GPIO\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01250\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM8\_TI1\_RMP\_COMP2\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_TISEL\_TI1SEL\_0\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{01254\ }
\DoxyCodeLine{01258\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM2\_TI4\_RMP\_GPIO\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01259\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM2\_TI4\_RMP\_COMP1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_TISEL\_TI4SEL\_0\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01260\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM2\_TI4\_RMP\_COMP2\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_TISEL\_TI4SEL\_1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01261\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM2\_TI4\_RMP\_COMP1\_COMP2\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_TISEL\_TI4SEL\_0\ |\ TIM\_TISEL\_TI4SEL\_1)\ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{01265\ }
\DoxyCodeLine{01269\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM3\_TI1\_RMP\_GPIO\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01270\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM3\_TI1\_RMP\_COMP1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_TISEL\_TI1SEL\_0\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01271\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM3\_TI1\_RMP\_COMP2\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_TISEL\_TI1SEL\_1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01272\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM3\_TI1\_RMP\_COMP1\_COMP2\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_TISEL\_TI1SEL\_0\ |\ TIM\_TISEL\_TI1SEL\_1)\ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{01276\ }
\DoxyCodeLine{01280\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM5\_TI1\_RMP\_GPIO\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01281\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM5\_TI1\_RMP\_CAN\_TMP\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_TISEL\_TI1SEL\_0\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01282\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM5\_TI1\_RMP\_CAN\_RTP\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_TISEL\_TI1SEL\_1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{01286\ }
\DoxyCodeLine{01290\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM12\_TI1\_RMP\_GPIO\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01291\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM12\_TI1\_RMP\_SPDIF\_FS\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_TISEL\_TI1SEL\_0\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{01295\ }
\DoxyCodeLine{01299\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM15\_TI1\_RMP\_GPIO\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01300\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM15\_TI1\_RMP\_TIM2\_CH1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_TISEL\_TI1SEL\_0\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01301\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM15\_TI1\_RMP\_TIM3\_CH1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_TISEL\_TI1SEL\_1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01302\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM15\_TI1\_RMP\_TIM4\_CH1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_TISEL\_TI1SEL\_0\ |\ TIM\_TISEL\_TI1SEL\_1)\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01303\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM15\_TI1\_RMP\_RCC\_LSE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_TISEL\_TI1SEL\_2)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01304\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM15\_TI1\_RMP\_RCC\_CSI\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_TISEL\_TI1SEL\_2\ |\ TIM\_TISEL\_TI1SEL\_0)\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01305\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM15\_TI1\_RMP\_RCC\_MCO2\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_TISEL\_TI1SEL\_2\ |\ TIM\_TISEL\_TI1SEL\_1)\ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{01309\ }
\DoxyCodeLine{01313\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM15\_TI2\_RMP\_GPIO\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01314\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM15\_TI2\_RMP\_TIM2\_CH2\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_TISEL\_TI2SEL\_0)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01315\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM15\_TI2\_RMP\_TIM3\_CH2\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_TISEL\_TI2SEL\_1)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01316\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM15\_TI2\_RMP\_TIM4\_CH2\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_TISEL\_TI2SEL\_0\ |\ TIM\_TISEL\_TI2SEL\_1)\ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{01320\ }
\DoxyCodeLine{01324\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM16\_TI1\_RMP\_GPIO\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01325\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM16\_TI1\_RMP\_RCC\_LSI\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_TISEL\_TI1SEL\_0\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01326\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM16\_TI1\_RMP\_RCC\_LSE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_TISEL\_TI1SEL\_1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01327\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM16\_TI1\_RMP\_WKUP\_IT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_TISEL\_TI1SEL\_0\ |\ TIM\_TISEL\_TI1SEL\_1)\ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{01331\ }
\DoxyCodeLine{01335\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM17\_TI1\_RMP\_GPIO\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01336\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM17\_TI1\_RMP\_SPDIF\_FS\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_TISEL\_TI1SEL\_0\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01337\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM17\_TI1\_RMP\_RCC\_HSE1MHZ\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_TISEL\_TI1SEL\_1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01338\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM17\_TI1\_RMP\_RCC\_MCO1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_TISEL\_TI1SEL\_0\ |\ TIM\_TISEL\_TI1SEL\_1)\ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{01342\ }
\DoxyCodeLine{01346\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM23\_TI4\_RMP\_GPIO\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01347\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM23\_TI4\_RMP\_COMP1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_TISEL\_TI4SEL\_0\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01348\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM23\_TI4\_RMP\_COMP2\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_TISEL\_TI4SEL\_1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01349\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM23\_TI4\_RMP\_COMP1\_COMP2\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_TISEL\_TI4SEL\_0\ |\ TIM\_TISEL\_TI4SEL\_1)\ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{01353\ }
\DoxyCodeLine{01357\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM24\_TI1\_RMP\_GPIO\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00000000U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01358\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM24\_TI1\_RMP\_CAN\_TMP\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_TISEL\_TI1SEL\_0\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01359\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM24\_TI1\_RMP\_CAN\_RTP\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_TISEL\_TI1SEL\_1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01360\ \textcolor{preprocessor}{\#define\ LL\_TIM\_TIM24\_TI1\_RMP\_CAN\_SOC\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (TIM\_TISEL\_TI4SEL\_0\ |\ TIM\_TISEL\_TI4SEL\_1)\ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{01364\ }
\DoxyCodeLine{01365\ \textcolor{preprocessor}{\#if\ defined(TIM\_BREAK\_INPUT\_SUPPORT)}\textcolor{preprocessor}{}}
\DoxyCodeLine{01369\ \textcolor{preprocessor}{\#define\ LL\_TIM\_BKIN\_SOURCE\_DFBK\ \ LL\_TIM\_BKIN\_SOURCE\_DF1BK}\textcolor{preprocessor}{}}
\DoxyCodeLine{01373\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ TIM\_BREAK\_INPUT\_SUPPORT\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{01374\ }
\DoxyCodeLine{01378\ }
\DoxyCodeLine{01379\ \textcolor{comment}{/*\ Exported\ macro\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
\DoxyCodeLine{01383\ }
\DoxyCodeLine{01394\ \textcolor{preprocessor}{\#define\ LL\_TIM\_WriteReg(\_\_INSTANCE\_\_,\ \_\_REG\_\_,\ \_\_VALUE\_\_)\ WRITE\_REG((\_\_INSTANCE\_\_)-\/>\_\_REG\_\_,\ (\_\_VALUE\_\_))}}
\DoxyCodeLine{01395\ }
\DoxyCodeLine{01402\ \textcolor{preprocessor}{\#define\ LL\_TIM\_ReadReg(\_\_INSTANCE\_\_,\ \_\_REG\_\_)\ READ\_REG((\_\_INSTANCE\_\_)-\/>\_\_REG\_\_)}\textcolor{preprocessor}{}}
\DoxyCodeLine{01406\ }
\DoxyCodeLine{01415\ \textcolor{preprocessor}{\#define\ \_\_LL\_TIM\_GETFLAG\_UIFCPY(\_\_CNT\_\_)\ \ \(\backslash\)}}
\DoxyCodeLine{01416\ \textcolor{preprocessor}{\ \ (READ\_BIT((\_\_CNT\_\_),\ TIM\_CNT\_UIFCPY)\ >>\ TIM\_CNT\_UIFCPY\_Pos)}}
\DoxyCodeLine{01417\ }
\DoxyCodeLine{01429\ \textcolor{preprocessor}{\#define\ \_\_LL\_TIM\_CALC\_DEADTIME(\_\_TIMCLK\_\_,\ \_\_CKD\_\_,\ \_\_DT\_\_)\ \ \(\backslash\)}}
\DoxyCodeLine{01430\ \textcolor{preprocessor}{\ \ (\ (((uint64\_t)((\_\_DT\_\_)*1000U))\ <\ ((DT\_DELAY\_1+1U)\ *\ TIM\_CALC\_DTS((\_\_TIMCLK\_\_),\ (\_\_CKD\_\_))))\ \ \ \ ?\ \ \(\backslash\)}}
\DoxyCodeLine{01431\ \textcolor{preprocessor}{\ \ \ \ (uint8\_t)(((uint64\_t)((\_\_DT\_\_)*1000U)\ /\ TIM\_CALC\_DTS((\_\_TIMCLK\_\_),\ (\_\_CKD\_\_)))\ \ \&\ DT\_DELAY\_1)\ :\ \ \ \ \ \ \(\backslash\)}}
\DoxyCodeLine{01432\ \textcolor{preprocessor}{\ \ \ \ (((uint64\_t)((\_\_DT\_\_)*1000U))\ <\ ((64U\ +\ (DT\_DELAY\_2+1U))\ *\ 2U\ *\ TIM\_CALC\_DTS((\_\_TIMCLK\_\_),\ (\_\_CKD\_\_))))\ \ ?\ \ \(\backslash\)}}
\DoxyCodeLine{01433\ \textcolor{preprocessor}{\ \ \ \ (uint8\_t)(DT\_RANGE\_2\ |\ ((uint8\_t)((uint8\_t)((((uint64\_t)((\_\_DT\_\_)*1000U))/\ TIM\_CALC\_DTS((\_\_TIMCLK\_\_),\ \ \ \(\backslash\)}}
\DoxyCodeLine{01434\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (\_\_CKD\_\_)))\ >>\ 1U)\ -\/\ (uint8\_t)\ 64)\ \&\ DT\_DELAY\_2))\ :\(\backslash\)}}
\DoxyCodeLine{01435\ \textcolor{preprocessor}{\ \ \ \ (((uint64\_t)((\_\_DT\_\_)*1000U))\ <\ ((32U\ +\ (DT\_DELAY\_3+1U))\ *\ 8U\ *\ TIM\_CALC\_DTS((\_\_TIMCLK\_\_),\ (\_\_CKD\_\_))))\ \ ?\ \ \(\backslash\)}}
\DoxyCodeLine{01436\ \textcolor{preprocessor}{\ \ \ \ (uint8\_t)(DT\_RANGE\_3\ |\ ((uint8\_t)((uint8\_t)(((((uint64\_t)(\_\_DT\_\_)*1000U))/\ TIM\_CALC\_DTS((\_\_TIMCLK\_\_),\ \ \(\backslash\)}}
\DoxyCodeLine{01437\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (\_\_CKD\_\_)))\ >>\ 3U)\ -\/\ (uint8\_t)\ 32)\ \&\ DT\_DELAY\_3))\ :\(\backslash\)}}
\DoxyCodeLine{01438\ \textcolor{preprocessor}{\ \ \ \ (((uint64\_t)((\_\_DT\_\_)*1000U))\ <\ ((32U\ +\ (DT\_DELAY\_4+1U))\ *\ 16U\ *\ TIM\_CALC\_DTS((\_\_TIMCLK\_\_),\ (\_\_CKD\_\_))))\ ?\ \ \(\backslash\)}}
\DoxyCodeLine{01439\ \textcolor{preprocessor}{\ \ \ \ (uint8\_t)(DT\_RANGE\_4\ |\ ((uint8\_t)((uint8\_t)(((((uint64\_t)(\_\_DT\_\_)*1000U))/\ TIM\_CALC\_DTS((\_\_TIMCLK\_\_),\ \ \(\backslash\)}}
\DoxyCodeLine{01440\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (\_\_CKD\_\_)))\ >>\ 4U)\ -\/\ (uint8\_t)\ 32)\ \&\ DT\_DELAY\_4))\ :\(\backslash\)}}
\DoxyCodeLine{01441\ \textcolor{preprocessor}{\ \ \ \ 0U)}}
\DoxyCodeLine{01442\ }
\DoxyCodeLine{01450\ \textcolor{preprocessor}{\#define\ \_\_LL\_TIM\_CALC\_PSC(\_\_TIMCLK\_\_,\ \_\_CNTCLK\_\_)\ \ \ \(\backslash\)}}
\DoxyCodeLine{01451\ \textcolor{preprocessor}{\ \ (((\_\_TIMCLK\_\_)\ >=\ (\_\_CNTCLK\_\_))\ ?\ (uint32\_t)((((\_\_TIMCLK\_\_)\ +\ (\_\_CNTCLK\_\_)/2U)/(\_\_CNTCLK\_\_))\ -\/\ 1U)\ :\ 0U)}}
\DoxyCodeLine{01452\ }
\DoxyCodeLine{01461\ \textcolor{preprocessor}{\#define\ \_\_LL\_TIM\_CALC\_ARR(\_\_TIMCLK\_\_,\ \_\_PSC\_\_,\ \_\_FREQ\_\_)\ \(\backslash\)}}
\DoxyCodeLine{01462\ \textcolor{preprocessor}{\ \ ((((\_\_TIMCLK\_\_)/((\_\_PSC\_\_)\ +\ 1U))\ >=\ (\_\_FREQ\_\_))\ ?\ (((\_\_TIMCLK\_\_)/((\_\_FREQ\_\_)\ *\ ((\_\_PSC\_\_)\ +\ 1U)))\ -\/\ 1U)\ :\ 0U)}}
\DoxyCodeLine{01463\ }
\DoxyCodeLine{01473\ \textcolor{preprocessor}{\#define\ \_\_LL\_TIM\_CALC\_DELAY(\_\_TIMCLK\_\_,\ \_\_PSC\_\_,\ \_\_DELAY\_\_)\ \ \(\backslash\)}}
\DoxyCodeLine{01474\ \textcolor{preprocessor}{\ \ ((uint32\_t)(((uint64\_t)(\_\_TIMCLK\_\_)\ *\ (uint64\_t)(\_\_DELAY\_\_))\ \(\backslash\)}}
\DoxyCodeLine{01475\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ /\ ((uint64\_t)1000000U\ *\ (uint64\_t)((\_\_PSC\_\_)\ +\ 1U))))}}
\DoxyCodeLine{01476\ }
\DoxyCodeLine{01487\ \textcolor{preprocessor}{\#define\ \_\_LL\_TIM\_CALC\_PULSE(\_\_TIMCLK\_\_,\ \_\_PSC\_\_,\ \_\_DELAY\_\_,\ \_\_PULSE\_\_)\ \ \(\backslash\)}}
\DoxyCodeLine{01488\ \textcolor{preprocessor}{\ \ ((uint32\_t)(\_\_LL\_TIM\_CALC\_DELAY((\_\_TIMCLK\_\_),\ (\_\_PSC\_\_),\ (\_\_PULSE\_\_))\ \(\backslash\)}}
\DoxyCodeLine{01489\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ +\ \_\_LL\_TIM\_CALC\_DELAY((\_\_TIMCLK\_\_),\ (\_\_PSC\_\_),\ (\_\_DELAY\_\_))))}}
\DoxyCodeLine{01490\ }
\DoxyCodeLine{01501\ \textcolor{preprocessor}{\#define\ \_\_LL\_TIM\_GET\_ICPSC\_RATIO(\_\_ICPSC\_\_)\ \ \(\backslash\)}}
\DoxyCodeLine{01502\ \textcolor{preprocessor}{\ \ ((uint32\_t)(0x01U\ <<\ (((\_\_ICPSC\_\_)\ >>\ 16U)\ >>\ TIM\_CCMR1\_IC1PSC\_Pos)))}}
\DoxyCodeLine{01503\ }
\DoxyCodeLine{01504\ }
\DoxyCodeLine{01508\ }
\DoxyCodeLine{01509\ \textcolor{comment}{/*\ Exported\ functions\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
\DoxyCodeLine{01513\ }
\DoxyCodeLine{01523\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_EnableCounter(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{01524\ \{}
\DoxyCodeLine{01525\ \ \ SET\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a9dafc8b03e8497203a8bb395db865328}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga93d86355e5e3b399ed45e1ca83abed2a}{TIM\_CR1\_CEN}});}
\DoxyCodeLine{01526\ \}}
\DoxyCodeLine{01527\ }
\DoxyCodeLine{01534\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_DisableCounter(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{01535\ \{}
\DoxyCodeLine{01536\ \ \ CLEAR\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a9dafc8b03e8497203a8bb395db865328}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga93d86355e5e3b399ed45e1ca83abed2a}{TIM\_CR1\_CEN}});}
\DoxyCodeLine{01537\ \}}
\DoxyCodeLine{01538\ }
\DoxyCodeLine{01545\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IsEnabledCounter(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{01546\ \{}
\DoxyCodeLine{01547\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a9dafc8b03e8497203a8bb395db865328}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga93d86355e5e3b399ed45e1ca83abed2a}{TIM\_CR1\_CEN}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga93d86355e5e3b399ed45e1ca83abed2a}{TIM\_CR1\_CEN}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{01548\ \}}
\DoxyCodeLine{01549\ }
\DoxyCodeLine{01556\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_EnableUpdateEvent(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{01557\ \{}
\DoxyCodeLine{01558\ \ \ CLEAR\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a9dafc8b03e8497203a8bb395db865328}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa4f2a9f0cf7b60e3c623af451f141f3c}{TIM\_CR1\_UDIS}});}
\DoxyCodeLine{01559\ \}}
\DoxyCodeLine{01560\ }
\DoxyCodeLine{01567\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_DisableUpdateEvent(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{01568\ \{}
\DoxyCodeLine{01569\ \ \ SET\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a9dafc8b03e8497203a8bb395db865328}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa4f2a9f0cf7b60e3c623af451f141f3c}{TIM\_CR1\_UDIS}});}
\DoxyCodeLine{01570\ \}}
\DoxyCodeLine{01571\ }
\DoxyCodeLine{01578\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IsEnabledUpdateEvent(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{01579\ \{}
\DoxyCodeLine{01580\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a9dafc8b03e8497203a8bb395db865328}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa4f2a9f0cf7b60e3c623af451f141f3c}{TIM\_CR1\_UDIS}})\ ==\ (uint32\_t)RESET)\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{01581\ \}}
\DoxyCodeLine{01582\ }
\DoxyCodeLine{01599\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_SetUpdateSource(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ UpdateSource)}
\DoxyCodeLine{01600\ \{}
\DoxyCodeLine{01601\ \ \ MODIFY\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a9dafc8b03e8497203a8bb395db865328}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga06c997c2c23e8bef7ca07579762c113b}{TIM\_CR1\_URS}},\ UpdateSource);}
\DoxyCodeLine{01602\ \}}
\DoxyCodeLine{01603\ }
\DoxyCodeLine{01612\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_GetUpdateSource(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{01613\ \{}
\DoxyCodeLine{01614\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a9dafc8b03e8497203a8bb395db865328}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga06c997c2c23e8bef7ca07579762c113b}{TIM\_CR1\_URS}}));}
\DoxyCodeLine{01615\ \}}
\DoxyCodeLine{01616\ }
\DoxyCodeLine{01626\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_SetOnePulseMode(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ OnePulseMode)}
\DoxyCodeLine{01627\ \{}
\DoxyCodeLine{01628\ \ \ MODIFY\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a9dafc8b03e8497203a8bb395db865328}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6d3d1488296350af6d36fbbf71905d29}{TIM\_CR1\_OPM}},\ OnePulseMode);}
\DoxyCodeLine{01629\ \}}
\DoxyCodeLine{01630\ }
\DoxyCodeLine{01639\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_GetOnePulseMode(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{01640\ \{}
\DoxyCodeLine{01641\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a9dafc8b03e8497203a8bb395db865328}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6d3d1488296350af6d36fbbf71905d29}{TIM\_CR1\_OPM}}));}
\DoxyCodeLine{01642\ \}}
\DoxyCodeLine{01643\ }
\DoxyCodeLine{01663\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_SetCounterMode(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ CounterMode)}
\DoxyCodeLine{01664\ \{}
\DoxyCodeLine{01665\ \ \ MODIFY\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a9dafc8b03e8497203a8bb395db865328}{CR1}},\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gacea10770904af189f3aaeb97b45722aa}{TIM\_CR1\_DIR}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga352b3c389bde13dd6049de0afdd874f1}{TIM\_CR1\_CMS}}),\ CounterMode);}
\DoxyCodeLine{01666\ \}}
\DoxyCodeLine{01667\ }
\DoxyCodeLine{01683\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_GetCounterMode(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{01684\ \{}
\DoxyCodeLine{01685\ \ \ uint32\_t\ counter\_mode;}
\DoxyCodeLine{01686\ }
\DoxyCodeLine{01687\ \ \ counter\_mode\ =\ (uint32\_t)(READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a9dafc8b03e8497203a8bb395db865328}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga352b3c389bde13dd6049de0afdd874f1}{TIM\_CR1\_CMS}}));}
\DoxyCodeLine{01688\ }
\DoxyCodeLine{01689\ \ \ \textcolor{keywordflow}{if}\ (counter\_mode\ ==\ 0U)}
\DoxyCodeLine{01690\ \ \ \{}
\DoxyCodeLine{01691\ \ \ \ \ counter\_mode\ =\ (uint32\_t)(READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a9dafc8b03e8497203a8bb395db865328}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gacea10770904af189f3aaeb97b45722aa}{TIM\_CR1\_DIR}}));}
\DoxyCodeLine{01692\ \ \ \}}
\DoxyCodeLine{01693\ }
\DoxyCodeLine{01694\ \ \ \textcolor{keywordflow}{return}\ counter\_mode;}
\DoxyCodeLine{01695\ \}}
\DoxyCodeLine{01696\ }
\DoxyCodeLine{01703\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_EnableARRPreload(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{01704\ \{}
\DoxyCodeLine{01705\ \ \ SET\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a9dafc8b03e8497203a8bb395db865328}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga4a3ad409f6b147cdcbafbfe29102f3fd}{TIM\_CR1\_ARPE}});}
\DoxyCodeLine{01706\ \}}
\DoxyCodeLine{01707\ }
\DoxyCodeLine{01714\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_DisableARRPreload(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{01715\ \{}
\DoxyCodeLine{01716\ \ \ CLEAR\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a9dafc8b03e8497203a8bb395db865328}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga4a3ad409f6b147cdcbafbfe29102f3fd}{TIM\_CR1\_ARPE}});}
\DoxyCodeLine{01717\ \}}
\DoxyCodeLine{01718\ }
\DoxyCodeLine{01725\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IsEnabledARRPreload(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{01726\ \{}
\DoxyCodeLine{01727\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a9dafc8b03e8497203a8bb395db865328}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga4a3ad409f6b147cdcbafbfe29102f3fd}{TIM\_CR1\_ARPE}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga4a3ad409f6b147cdcbafbfe29102f3fd}{TIM\_CR1\_ARPE}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{01728\ \}}
\DoxyCodeLine{01729\ }
\DoxyCodeLine{01744\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_SetClockDivision(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ ClockDivision)}
\DoxyCodeLine{01745\ \{}
\DoxyCodeLine{01746\ \ \ MODIFY\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a9dafc8b03e8497203a8bb395db865328}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gacacc4ff7e5b75fd2e4e6b672ccd33a72}{TIM\_CR1\_CKD}},\ ClockDivision);}
\DoxyCodeLine{01747\ \}}
\DoxyCodeLine{01748\ }
\DoxyCodeLine{01762\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_GetClockDivision(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{01763\ \{}
\DoxyCodeLine{01764\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a9dafc8b03e8497203a8bb395db865328}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gacacc4ff7e5b75fd2e4e6b672ccd33a72}{TIM\_CR1\_CKD}}));}
\DoxyCodeLine{01765\ \}}
\DoxyCodeLine{01766\ }
\DoxyCodeLine{01776\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_SetCounter(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ Counter)}
\DoxyCodeLine{01777\ \{}
\DoxyCodeLine{01778\ \ \ WRITE\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a6fdd2a7fb88d28670b472aaac0d9d262}{CNT}},\ Counter);}
\DoxyCodeLine{01779\ \}}
\DoxyCodeLine{01780\ }
\DoxyCodeLine{01789\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_GetCounter(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{01790\ \{}
\DoxyCodeLine{01791\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a6fdd2a7fb88d28670b472aaac0d9d262}{CNT}}));}
\DoxyCodeLine{01792\ \}}
\DoxyCodeLine{01793\ }
\DoxyCodeLine{01802\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_GetDirection(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{01803\ \{}
\DoxyCodeLine{01804\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a9dafc8b03e8497203a8bb395db865328}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gacea10770904af189f3aaeb97b45722aa}{TIM\_CR1\_DIR}}));}
\DoxyCodeLine{01805\ \}}
\DoxyCodeLine{01806\ }
\DoxyCodeLine{01818\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_SetPrescaler(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ Prescaler)}
\DoxyCodeLine{01819\ \{}
\DoxyCodeLine{01820\ \ \ WRITE\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_ad03c852f58077a11e75f8af42fa6d921}{PSC}},\ Prescaler);}
\DoxyCodeLine{01821\ \}}
\DoxyCodeLine{01822\ }
\DoxyCodeLine{01829\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_GetPrescaler(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{01830\ \{}
\DoxyCodeLine{01831\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_ad03c852f58077a11e75f8af42fa6d921}{PSC}}));}
\DoxyCodeLine{01832\ \}}
\DoxyCodeLine{01833\ }
\DoxyCodeLine{01845\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_SetAutoReload(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ AutoReload)}
\DoxyCodeLine{01846\ \{}
\DoxyCodeLine{01847\ \ \ WRITE\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a6a42766a6ca3c7fe10a810ebd6b9d627}{ARR}},\ AutoReload);}
\DoxyCodeLine{01848\ \}}
\DoxyCodeLine{01849\ }
\DoxyCodeLine{01858\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_GetAutoReload(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{01859\ \{}
\DoxyCodeLine{01860\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a6a42766a6ca3c7fe10a810ebd6b9d627}{ARR}}));}
\DoxyCodeLine{01861\ \}}
\DoxyCodeLine{01862\ }
\DoxyCodeLine{01873\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_SetRepetitionCounter(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ RepetitionCounter)}
\DoxyCodeLine{01874\ \{}
\DoxyCodeLine{01875\ \ \ WRITE\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_ad432e2a315abf68e6c295fb4ebc37534}{RCR}},\ RepetitionCounter);}
\DoxyCodeLine{01876\ \}}
\DoxyCodeLine{01877\ }
\DoxyCodeLine{01886\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_GetRepetitionCounter(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{01887\ \{}
\DoxyCodeLine{01888\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_ad432e2a315abf68e6c295fb4ebc37534}{RCR}}));}
\DoxyCodeLine{01889\ \}}
\DoxyCodeLine{01890\ }
\DoxyCodeLine{01899\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_EnableUIFRemap(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{01900\ \{}
\DoxyCodeLine{01901\ \ \ SET\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a9dafc8b03e8497203a8bb395db865328}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf0c8b29f2a8d1426cf31270643d811c7}{TIM\_CR1\_UIFREMAP}});}
\DoxyCodeLine{01902\ \}}
\DoxyCodeLine{01903\ }
\DoxyCodeLine{01910\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_DisableUIFRemap(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{01911\ \{}
\DoxyCodeLine{01912\ \ \ CLEAR\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a9dafc8b03e8497203a8bb395db865328}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf0c8b29f2a8d1426cf31270643d811c7}{TIM\_CR1\_UIFREMAP}});}
\DoxyCodeLine{01913\ \}}
\DoxyCodeLine{01914\ }
\DoxyCodeLine{01920\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IsActiveUIFCPY(\textcolor{keyword}{const}\ uint32\_t\ Counter)}
\DoxyCodeLine{01921\ \{}
\DoxyCodeLine{01922\ \ \ \textcolor{keywordflow}{return}\ (((Counter\ \&\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga9060f1ca4c5df1ab6e70af699ac71a16}{TIM\_CNT\_UIFCPY}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga9060f1ca4c5df1ab6e70af699ac71a16}{TIM\_CNT\_UIFCPY}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{01923\ \}}
\DoxyCodeLine{01924\ }
\DoxyCodeLine{01928\ }
\DoxyCodeLine{01943\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_CC\_EnablePreload(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{01944\ \{}
\DoxyCodeLine{01945\ \ \ SET\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a6b1ae85138ed91686bf63699c61ef835}{CR2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaae22c9c1197107d6fa629f419a29541e}{TIM\_CR2\_CCPC}});}
\DoxyCodeLine{01946\ \}}
\DoxyCodeLine{01947\ }
\DoxyCodeLine{01956\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_CC\_DisablePreload(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{01957\ \{}
\DoxyCodeLine{01958\ \ \ CLEAR\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a6b1ae85138ed91686bf63699c61ef835}{CR2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaae22c9c1197107d6fa629f419a29541e}{TIM\_CR2\_CCPC}});}
\DoxyCodeLine{01959\ \}}
\DoxyCodeLine{01960\ }
\DoxyCodeLine{01967\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_CC\_IsEnabledPreload(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{01968\ \{}
\DoxyCodeLine{01969\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a6b1ae85138ed91686bf63699c61ef835}{CR2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaae22c9c1197107d6fa629f419a29541e}{TIM\_CR2\_CCPC}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaae22c9c1197107d6fa629f419a29541e}{TIM\_CR2\_CCPC}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{01970\ \}}
\DoxyCodeLine{01971\ }
\DoxyCodeLine{01983\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_CC\_SetUpdate(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ CCUpdateSource)}
\DoxyCodeLine{01984\ \{}
\DoxyCodeLine{01985\ \ \ MODIFY\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a6b1ae85138ed91686bf63699c61ef835}{CR2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf0328c1339b2b1633ef7a8db4c02d0d5}{TIM\_CR2\_CCUS}},\ CCUpdateSource);}
\DoxyCodeLine{01986\ \}}
\DoxyCodeLine{01987\ }
\DoxyCodeLine{01997\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_CC\_SetDMAReqTrigger(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ DMAReqTrigger)}
\DoxyCodeLine{01998\ \{}
\DoxyCodeLine{01999\ \ \ MODIFY\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a6b1ae85138ed91686bf63699c61ef835}{CR2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gade656832d3ec303a2a7a422638dd560e}{TIM\_CR2\_CCDS}},\ DMAReqTrigger);}
\DoxyCodeLine{02000\ \}}
\DoxyCodeLine{02001\ }
\DoxyCodeLine{02010\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_CC\_GetDMAReqTrigger(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{02011\ \{}
\DoxyCodeLine{02012\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a6b1ae85138ed91686bf63699c61ef835}{CR2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gade656832d3ec303a2a7a422638dd560e}{TIM\_CR2\_CCDS}}));}
\DoxyCodeLine{02013\ \}}
\DoxyCodeLine{02014\ }
\DoxyCodeLine{02029\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_CC\_SetLockLevel(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ LockLevel)}
\DoxyCodeLine{02030\ \{}
\DoxyCodeLine{02031\ \ \ MODIFY\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a137d3523b60951eca1e4130257b2b23d}{BDTR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga7e4215d17f0548dfcf0b15fe4d0f4651}{TIM\_BDTR\_LOCK}},\ LockLevel);}
\DoxyCodeLine{02032\ \}}
\DoxyCodeLine{02033\ }
\DoxyCodeLine{02058\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_CC\_EnableChannel(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ Channels)}
\DoxyCodeLine{02059\ \{}
\DoxyCodeLine{02060\ \ \ SET\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_ad7271cc1eec9ef16e4ee5401626c0b3b}{CCER}},\ Channels);}
\DoxyCodeLine{02061\ \}}
\DoxyCodeLine{02062\ }
\DoxyCodeLine{02087\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_CC\_DisableChannel(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ Channels)}
\DoxyCodeLine{02088\ \{}
\DoxyCodeLine{02089\ \ \ CLEAR\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_ad7271cc1eec9ef16e4ee5401626c0b3b}{CCER}},\ Channels);}
\DoxyCodeLine{02090\ \}}
\DoxyCodeLine{02091\ }
\DoxyCodeLine{02116\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_CC\_IsEnabledChannel(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ Channels)}
\DoxyCodeLine{02117\ \{}
\DoxyCodeLine{02118\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_ad7271cc1eec9ef16e4ee5401626c0b3b}{CCER}},\ Channels)\ ==\ (Channels))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02119\ \}}
\DoxyCodeLine{02120\ }
\DoxyCodeLine{02124\ }
\DoxyCodeLine{02161\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_OC\_ConfigOutput(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ Channel,\ uint32\_t\ Configuration)}
\DoxyCodeLine{02162\ \{}
\DoxyCodeLine{02163\ \ \ uint8\_t\ iChannel\ =\ TIM\_GET\_CHANNEL\_INDEX(Channel);}
\DoxyCodeLine{02164\ \ \ \mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *pReg\ =\ (\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *)((uint32\_t)((uint32\_t)(\&TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a0f2291e7efdf3222689ef13e9be2ea4a}{CCMR1}})\ +\ OFFSET\_TAB\_CCMRx[iChannel]));}
\DoxyCodeLine{02165\ \ \ CLEAR\_BIT(*pReg,\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga95291df1eaf532c5c996d176648938eb}{TIM\_CCMR1\_CC1S}}\ <<\ SHIFT\_TAB\_OCxx[iChannel]));}
\DoxyCodeLine{02166\ \ \ MODIFY\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_ad7271cc1eec9ef16e4ee5401626c0b3b}{CCER}},\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga0ca0aedba14241caff739afb3c3ee291}{TIM\_CCER\_CC1P}}\ <<\ SHIFT\_TAB\_CCxP[iChannel]),}
\DoxyCodeLine{02167\ \ \ \ \ \ \ \ \ \ \ \ \ \ (Configuration\ \&\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga0ca0aedba14241caff739afb3c3ee291}{TIM\_CCER\_CC1P}})\ <<\ SHIFT\_TAB\_CCxP[iChannel]);}
\DoxyCodeLine{02168\ \ \ MODIFY\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a6b1ae85138ed91686bf63699c61ef835}{CR2}},\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga31b26bf058f88d771c33aff85ec89358}{TIM\_CR2\_OIS1}}\ <<\ SHIFT\_TAB\_OISx[iChannel]),}
\DoxyCodeLine{02169\ \ \ \ \ \ \ \ \ \ \ \ \ \ (Configuration\ \&\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga31b26bf058f88d771c33aff85ec89358}{TIM\_CR2\_OIS1}})\ <<\ SHIFT\_TAB\_OISx[iChannel]);}
\DoxyCodeLine{02170\ \}}
\DoxyCodeLine{02171\ }
\DoxyCodeLine{02206\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_OC\_SetMode(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ Channel,\ uint32\_t\ Mode)}
\DoxyCodeLine{02207\ \{}
\DoxyCodeLine{02208\ \ \ uint8\_t\ iChannel\ =\ TIM\_GET\_CHANNEL\_INDEX(Channel);}
\DoxyCodeLine{02209\ \ \ \mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *pReg\ =\ (\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *)((uint32\_t)((uint32\_t)(\&TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a0f2291e7efdf3222689ef13e9be2ea4a}{CCMR1}})\ +\ OFFSET\_TAB\_CCMRx[iChannel]));}
\DoxyCodeLine{02210\ \ \ MODIFY\_REG(*pReg,\ ((\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6ddb3dc889733e71d812baa3873cb13b}{TIM\_CCMR1\_OC1M}}\ \ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga95291df1eaf532c5c996d176648938eb}{TIM\_CCMR1\_CC1S}})\ <<\ SHIFT\_TAB\_OCxx[iChannel]),\ Mode\ <<\ SHIFT\_TAB\_OCxx[iChannel]);}
\DoxyCodeLine{02211\ \}}
\DoxyCodeLine{02212\ }
\DoxyCodeLine{02245\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_OC\_GetMode(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ Channel)}
\DoxyCodeLine{02246\ \{}
\DoxyCodeLine{02247\ \ \ uint8\_t\ iChannel\ =\ TIM\_GET\_CHANNEL\_INDEX(Channel);}
\DoxyCodeLine{02248\ \ \ \textcolor{keyword}{const}\ \mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *pReg\ =\ (\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *)((uint32\_t)((uint32\_t)(\&TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a0f2291e7efdf3222689ef13e9be2ea4a}{CCMR1}})\ +\ OFFSET\_TAB\_CCMRx[iChannel]));}
\DoxyCodeLine{02249\ \ \ \textcolor{keywordflow}{return}\ (READ\_BIT(*pReg,\ ((\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6ddb3dc889733e71d812baa3873cb13b}{TIM\_CCMR1\_OC1M}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga95291df1eaf532c5c996d176648938eb}{TIM\_CCMR1\_CC1S}})\ <<\ SHIFT\_TAB\_OCxx[iChannel]))\ >>\ SHIFT\_TAB\_OCxx[iChannel]);}
\DoxyCodeLine{02250\ \}}
\DoxyCodeLine{02251\ }
\DoxyCodeLine{02279\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_OC\_SetPolarity(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ Channel,\ uint32\_t\ Polarity)}
\DoxyCodeLine{02280\ \{}
\DoxyCodeLine{02281\ \ \ uint8\_t\ iChannel\ =\ TIM\_GET\_CHANNEL\_INDEX(Channel);}
\DoxyCodeLine{02282\ \ \ MODIFY\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_ad7271cc1eec9ef16e4ee5401626c0b3b}{CCER}},\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga0ca0aedba14241caff739afb3c3ee291}{TIM\_CCER\_CC1P}}\ <<\ SHIFT\_TAB\_CCxP[iChannel]),\ \ Polarity\ <<\ SHIFT\_TAB\_CCxP[iChannel]);}
\DoxyCodeLine{02283\ \}}
\DoxyCodeLine{02284\ }
\DoxyCodeLine{02311\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_OC\_GetPolarity(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ Channel)}
\DoxyCodeLine{02312\ \{}
\DoxyCodeLine{02313\ \ \ uint8\_t\ iChannel\ =\ TIM\_GET\_CHANNEL\_INDEX(Channel);}
\DoxyCodeLine{02314\ \ \ \textcolor{keywordflow}{return}\ (READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_ad7271cc1eec9ef16e4ee5401626c0b3b}{CCER}},\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga0ca0aedba14241caff739afb3c3ee291}{TIM\_CCER\_CC1P}}\ <<\ SHIFT\_TAB\_CCxP[iChannel]))\ >>\ SHIFT\_TAB\_CCxP[iChannel]);}
\DoxyCodeLine{02315\ \}}
\DoxyCodeLine{02316\ }
\DoxyCodeLine{02348\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_OC\_SetIdleState(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ Channel,\ uint32\_t\ IdleState)}
\DoxyCodeLine{02349\ \{}
\DoxyCodeLine{02350\ \ \ uint8\_t\ iChannel\ =\ TIM\_GET\_CHANNEL\_INDEX(Channel);}
\DoxyCodeLine{02351\ \ \ MODIFY\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a6b1ae85138ed91686bf63699c61ef835}{CR2}},\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga31b26bf058f88d771c33aff85ec89358}{TIM\_CR2\_OIS1}}\ <<\ SHIFT\_TAB\_OISx[iChannel]),\ \ IdleState\ <<\ SHIFT\_TAB\_OISx[iChannel]);}
\DoxyCodeLine{02352\ \}}
\DoxyCodeLine{02353\ }
\DoxyCodeLine{02380\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_OC\_GetIdleState(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ Channel)}
\DoxyCodeLine{02381\ \{}
\DoxyCodeLine{02382\ \ \ uint8\_t\ iChannel\ =\ TIM\_GET\_CHANNEL\_INDEX(Channel);}
\DoxyCodeLine{02383\ \ \ \textcolor{keywordflow}{return}\ (READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a6b1ae85138ed91686bf63699c61ef835}{CR2}},\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga31b26bf058f88d771c33aff85ec89358}{TIM\_CR2\_OIS1}}\ <<\ SHIFT\_TAB\_OISx[iChannel]))\ >>\ SHIFT\_TAB\_OISx[iChannel]);}
\DoxyCodeLine{02384\ \}}
\DoxyCodeLine{02385\ }
\DoxyCodeLine{02405\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_OC\_EnableFast(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ Channel)}
\DoxyCodeLine{02406\ \{}
\DoxyCodeLine{02407\ \ \ uint8\_t\ iChannel\ =\ TIM\_GET\_CHANNEL\_INDEX(Channel);}
\DoxyCodeLine{02408\ \ \ \mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *pReg\ =\ (\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *)((uint32\_t)((uint32\_t)(\&TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a0f2291e7efdf3222689ef13e9be2ea4a}{CCMR1}})\ +\ OFFSET\_TAB\_CCMRx[iChannel]));}
\DoxyCodeLine{02409\ \ \ SET\_BIT(*pReg,\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gab9c5878e85ce02c22d8a374deebd1b6e}{TIM\_CCMR1\_OC1FE}}\ <<\ SHIFT\_TAB\_OCxx[iChannel]));}
\DoxyCodeLine{02410\ }
\DoxyCodeLine{02411\ \}}
\DoxyCodeLine{02412\ }
\DoxyCodeLine{02431\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_OC\_DisableFast(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ Channel)}
\DoxyCodeLine{02432\ \{}
\DoxyCodeLine{02433\ \ \ uint8\_t\ iChannel\ =\ TIM\_GET\_CHANNEL\_INDEX(Channel);}
\DoxyCodeLine{02434\ \ \ \mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *pReg\ =\ (\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *)((uint32\_t)((uint32\_t)(\&TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a0f2291e7efdf3222689ef13e9be2ea4a}{CCMR1}})\ +\ OFFSET\_TAB\_CCMRx[iChannel]));}
\DoxyCodeLine{02435\ \ \ CLEAR\_BIT(*pReg,\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gab9c5878e85ce02c22d8a374deebd1b6e}{TIM\_CCMR1\_OC1FE}}\ <<\ SHIFT\_TAB\_OCxx[iChannel]));}
\DoxyCodeLine{02436\ }
\DoxyCodeLine{02437\ \}}
\DoxyCodeLine{02438\ }
\DoxyCodeLine{02457\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_OC\_IsEnabledFast(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ Channel)}
\DoxyCodeLine{02458\ \{}
\DoxyCodeLine{02459\ \ \ uint8\_t\ iChannel\ =\ TIM\_GET\_CHANNEL\_INDEX(Channel);}
\DoxyCodeLine{02460\ \ \ \textcolor{keyword}{const}\ \mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *pReg\ =\ (\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *)((uint32\_t)((uint32\_t)(\&TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a0f2291e7efdf3222689ef13e9be2ea4a}{CCMR1}})\ +\ OFFSET\_TAB\_CCMRx[iChannel]));}
\DoxyCodeLine{02461\ \ \ uint32\_t\ bitfield\ =\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gab9c5878e85ce02c22d8a374deebd1b6e}{TIM\_CCMR1\_OC1FE}}\ <<\ SHIFT\_TAB\_OCxx[iChannel];}
\DoxyCodeLine{02462\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(*pReg,\ bitfield)\ ==\ bitfield)\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02463\ \}}
\DoxyCodeLine{02464\ }
\DoxyCodeLine{02483\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_OC\_EnablePreload(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ Channel)}
\DoxyCodeLine{02484\ \{}
\DoxyCodeLine{02485\ \ \ uint8\_t\ iChannel\ =\ TIM\_GET\_CHANNEL\_INDEX(Channel);}
\DoxyCodeLine{02486\ \ \ \mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *pReg\ =\ (\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *)((uint32\_t)((uint32\_t)(\&TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a0f2291e7efdf3222689ef13e9be2ea4a}{CCMR1}})\ +\ OFFSET\_TAB\_CCMRx[iChannel]));}
\DoxyCodeLine{02487\ \ \ SET\_BIT(*pReg,\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga1aa54ddf87a4b339881a8d5368ec80eb}{TIM\_CCMR1\_OC1PE}}\ <<\ SHIFT\_TAB\_OCxx[iChannel]));}
\DoxyCodeLine{02488\ \}}
\DoxyCodeLine{02489\ }
\DoxyCodeLine{02508\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_OC\_DisablePreload(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ Channel)}
\DoxyCodeLine{02509\ \{}
\DoxyCodeLine{02510\ \ \ uint8\_t\ iChannel\ =\ TIM\_GET\_CHANNEL\_INDEX(Channel);}
\DoxyCodeLine{02511\ \ \ \mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *pReg\ =\ (\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *)((uint32\_t)((uint32\_t)(\&TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a0f2291e7efdf3222689ef13e9be2ea4a}{CCMR1}})\ +\ OFFSET\_TAB\_CCMRx[iChannel]));}
\DoxyCodeLine{02512\ \ \ CLEAR\_BIT(*pReg,\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga1aa54ddf87a4b339881a8d5368ec80eb}{TIM\_CCMR1\_OC1PE}}\ <<\ SHIFT\_TAB\_OCxx[iChannel]));}
\DoxyCodeLine{02513\ \}}
\DoxyCodeLine{02514\ }
\DoxyCodeLine{02533\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_OC\_IsEnabledPreload(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ Channel)}
\DoxyCodeLine{02534\ \{}
\DoxyCodeLine{02535\ \ \ uint8\_t\ iChannel\ =\ TIM\_GET\_CHANNEL\_INDEX(Channel);}
\DoxyCodeLine{02536\ \ \ \textcolor{keyword}{const}\ \mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *pReg\ =\ (\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *)((uint32\_t)((uint32\_t)(\&TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a0f2291e7efdf3222689ef13e9be2ea4a}{CCMR1}})\ +\ OFFSET\_TAB\_CCMRx[iChannel]));}
\DoxyCodeLine{02537\ \ \ uint32\_t\ bitfield\ =\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga1aa54ddf87a4b339881a8d5368ec80eb}{TIM\_CCMR1\_OC1PE}}\ <<\ SHIFT\_TAB\_OCxx[iChannel];}
\DoxyCodeLine{02538\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(*pReg,\ bitfield)\ ==\ bitfield)\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02539\ \}}
\DoxyCodeLine{02540\ }
\DoxyCodeLine{02562\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_OC\_EnableClear(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ Channel)}
\DoxyCodeLine{02563\ \{}
\DoxyCodeLine{02564\ \ \ uint8\_t\ iChannel\ =\ TIM\_GET\_CHANNEL\_INDEX(Channel);}
\DoxyCodeLine{02565\ \ \ \mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *pReg\ =\ (\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *)((uint32\_t)((uint32\_t)(\&TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a0f2291e7efdf3222689ef13e9be2ea4a}{CCMR1}})\ +\ OFFSET\_TAB\_CCMRx[iChannel]));}
\DoxyCodeLine{02566\ \ \ SET\_BIT(*pReg,\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga8f44c50cf9928d2afab014e2ca29baba}{TIM\_CCMR1\_OC1CE}}\ <<\ SHIFT\_TAB\_OCxx[iChannel]));}
\DoxyCodeLine{02567\ \}}
\DoxyCodeLine{02568\ }
\DoxyCodeLine{02589\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_OC\_DisableClear(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ Channel)}
\DoxyCodeLine{02590\ \{}
\DoxyCodeLine{02591\ \ \ uint8\_t\ iChannel\ =\ TIM\_GET\_CHANNEL\_INDEX(Channel);}
\DoxyCodeLine{02592\ \ \ \mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *pReg\ =\ (\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *)((uint32\_t)((uint32\_t)(\&TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a0f2291e7efdf3222689ef13e9be2ea4a}{CCMR1}})\ +\ OFFSET\_TAB\_CCMRx[iChannel]));}
\DoxyCodeLine{02593\ \ \ CLEAR\_BIT(*pReg,\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga8f44c50cf9928d2afab014e2ca29baba}{TIM\_CCMR1\_OC1CE}}\ <<\ SHIFT\_TAB\_OCxx[iChannel]));}
\DoxyCodeLine{02594\ \}}
\DoxyCodeLine{02595\ }
\DoxyCodeLine{02618\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_OC\_IsEnabledClear(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ Channel)}
\DoxyCodeLine{02619\ \{}
\DoxyCodeLine{02620\ \ \ uint8\_t\ iChannel\ =\ TIM\_GET\_CHANNEL\_INDEX(Channel);}
\DoxyCodeLine{02621\ \ \ \textcolor{keyword}{const}\ \mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *pReg\ =\ (\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *)((uint32\_t)((uint32\_t)(\&TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a0f2291e7efdf3222689ef13e9be2ea4a}{CCMR1}})\ +\ OFFSET\_TAB\_CCMRx[iChannel]));}
\DoxyCodeLine{02622\ \ \ uint32\_t\ bitfield\ =\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga8f44c50cf9928d2afab014e2ca29baba}{TIM\_CCMR1\_OC1CE}}\ <<\ SHIFT\_TAB\_OCxx[iChannel];}
\DoxyCodeLine{02623\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(*pReg,\ bitfield)\ ==\ bitfield)\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02624\ \}}
\DoxyCodeLine{02625\ }
\DoxyCodeLine{02637\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_OC\_SetDeadTime(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ DeadTime)}
\DoxyCodeLine{02638\ \{}
\DoxyCodeLine{02639\ \ \ MODIFY\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a137d3523b60951eca1e4130257b2b23d}{BDTR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gabcf985e9c78f15e1e44b2bc4d2bafc67}{TIM\_BDTR\_DTG}},\ DeadTime);}
\DoxyCodeLine{02640\ \}}
\DoxyCodeLine{02641\ }
\DoxyCodeLine{02654\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_OC\_SetCompareCH1(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ CompareValue)}
\DoxyCodeLine{02655\ \{}
\DoxyCodeLine{02656\ \ \ WRITE\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a0dd9c06729a5eb6179c6d0d60faca7ed}{CCR1}},\ CompareValue);}
\DoxyCodeLine{02657\ \}}
\DoxyCodeLine{02658\ }
\DoxyCodeLine{02671\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_OC\_SetCompareCH2(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ CompareValue)}
\DoxyCodeLine{02672\ \{}
\DoxyCodeLine{02673\ \ \ WRITE\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a4d1171e9a61538424b8ef1f2571986d0}{CCR2}},\ CompareValue);}
\DoxyCodeLine{02674\ \}}
\DoxyCodeLine{02675\ }
\DoxyCodeLine{02688\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_OC\_SetCompareCH3(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ CompareValue)}
\DoxyCodeLine{02689\ \{}
\DoxyCodeLine{02690\ \ \ WRITE\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_ac83441bfb8d0287080dcbd945a272a74}{CCR3}},\ CompareValue);}
\DoxyCodeLine{02691\ \}}
\DoxyCodeLine{02692\ }
\DoxyCodeLine{02705\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_OC\_SetCompareCH4(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ CompareValue)}
\DoxyCodeLine{02706\ \{}
\DoxyCodeLine{02707\ \ \ WRITE\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a5ba381c3f312fdf5e0b4119641b3b0aa}{CCR4}},\ CompareValue);}
\DoxyCodeLine{02708\ \}}
\DoxyCodeLine{02709\ }
\DoxyCodeLine{02719\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_OC\_SetCompareCH5(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ CompareValue)}
\DoxyCodeLine{02720\ \{}
\DoxyCodeLine{02721\ \ \ MODIFY\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_af30dc563e6c1b7b7e01e393feb484080}{CCR5}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga57a4e24f3276f4c908874940657dc7e7}{TIM\_CCR5\_CCR5}},\ CompareValue);}
\DoxyCodeLine{02722\ \}}
\DoxyCodeLine{02723\ }
\DoxyCodeLine{02733\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_OC\_SetCompareCH6(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ CompareValue)}
\DoxyCodeLine{02734\ \{}
\DoxyCodeLine{02735\ \ \ WRITE\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a374f851b5f1097a3ebd3f494ded6512a}{CCR6}},\ CompareValue);}
\DoxyCodeLine{02736\ \}}
\DoxyCodeLine{02737\ }
\DoxyCodeLine{02749\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_OC\_GetCompareCH1(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{02750\ \{}
\DoxyCodeLine{02751\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a0dd9c06729a5eb6179c6d0d60faca7ed}{CCR1}}));}
\DoxyCodeLine{02752\ \}}
\DoxyCodeLine{02753\ }
\DoxyCodeLine{02765\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_OC\_GetCompareCH2(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{02766\ \{}
\DoxyCodeLine{02767\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a4d1171e9a61538424b8ef1f2571986d0}{CCR2}}));}
\DoxyCodeLine{02768\ \}}
\DoxyCodeLine{02769\ }
\DoxyCodeLine{02781\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_OC\_GetCompareCH3(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{02782\ \{}
\DoxyCodeLine{02783\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_ac83441bfb8d0287080dcbd945a272a74}{CCR3}}));}
\DoxyCodeLine{02784\ \}}
\DoxyCodeLine{02785\ }
\DoxyCodeLine{02797\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_OC\_GetCompareCH4(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{02798\ \{}
\DoxyCodeLine{02799\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a5ba381c3f312fdf5e0b4119641b3b0aa}{CCR4}}));}
\DoxyCodeLine{02800\ \}}
\DoxyCodeLine{02801\ }
\DoxyCodeLine{02810\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_OC\_GetCompareCH5(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{02811\ \{}
\DoxyCodeLine{02812\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_af30dc563e6c1b7b7e01e393feb484080}{CCR5}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga57a4e24f3276f4c908874940657dc7e7}{TIM\_CCR5\_CCR5}}));}
\DoxyCodeLine{02813\ \}}
\DoxyCodeLine{02814\ }
\DoxyCodeLine{02823\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_OC\_GetCompareCH6(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{02824\ \{}
\DoxyCodeLine{02825\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a374f851b5f1097a3ebd3f494ded6512a}{CCR6}}));}
\DoxyCodeLine{02826\ \}}
\DoxyCodeLine{02827\ }
\DoxyCodeLine{02843\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_SetCH5CombinedChannels(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ GroupCH5)}
\DoxyCodeLine{02844\ \{}
\DoxyCodeLine{02845\ \ \ MODIFY\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_af30dc563e6c1b7b7e01e393feb484080}{CCR5}},\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaaaf84ef0edc60a2bb1d724fd28ae522e}{TIM\_CCR5\_GC5C3}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga66b51c31aab6f353303cffb10593a027}{TIM\_CCR5\_GC5C2}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gadce130a8f74c02de0f6e2f8cb0f16b6e}{TIM\_CCR5\_GC5C1}}),\ GroupCH5);}
\DoxyCodeLine{02846\ \}}
\DoxyCodeLine{02847\ }
\DoxyCodeLine{02851\ }
\DoxyCodeLine{02890\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_IC\_Config(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ Channel,\ uint32\_t\ Configuration)}
\DoxyCodeLine{02891\ \{}
\DoxyCodeLine{02892\ \ \ uint8\_t\ iChannel\ =\ TIM\_GET\_CHANNEL\_INDEX(Channel);}
\DoxyCodeLine{02893\ \ \ \mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *pReg\ =\ (\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *)((uint32\_t)((uint32\_t)(\&TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a0f2291e7efdf3222689ef13e9be2ea4a}{CCMR1}})\ +\ OFFSET\_TAB\_CCMRx[iChannel]));}
\DoxyCodeLine{02894\ \ \ MODIFY\_REG(*pReg,\ ((\mbox{\hyperlink{group___peripheral___registers___bits___definition_gab0ee123675d8b8f98b5a6eeeccf37912}{TIM\_CCMR1\_IC1F}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gab46b7186665f5308cd2ca52acfb63e72}{TIM\_CCMR1\_IC1PSC}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga95291df1eaf532c5c996d176648938eb}{TIM\_CCMR1\_CC1S}})\ <<\ SHIFT\_TAB\_ICxx[iChannel]),}
\DoxyCodeLine{02895\ \ \ \ \ \ \ \ \ \ \ \ \ \ ((Configuration\ >>\ 16U)\ \&\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gab0ee123675d8b8f98b5a6eeeccf37912}{TIM\_CCMR1\_IC1F}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gab46b7186665f5308cd2ca52acfb63e72}{TIM\_CCMR1\_IC1PSC}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga95291df1eaf532c5c996d176648938eb}{TIM\_CCMR1\_CC1S}}))\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \(\backslash\)}
\DoxyCodeLine{02896\ \ \ \ \ \ \ \ \ \ \ \ \ \ <<\ SHIFT\_TAB\_ICxx[iChannel]);}
\DoxyCodeLine{02897\ \ \ MODIFY\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_ad7271cc1eec9ef16e4ee5401626c0b3b}{CCER}},\ ((\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga403fc501d4d8de6cabee6b07acb81a36}{TIM\_CCER\_CC1NP}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga0ca0aedba14241caff739afb3c3ee291}{TIM\_CCER\_CC1P}})\ <<\ SHIFT\_TAB\_CCxP[iChannel]),}
\DoxyCodeLine{02898\ \ \ \ \ \ \ \ \ \ \ \ \ \ (Configuration\ \&\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga403fc501d4d8de6cabee6b07acb81a36}{TIM\_CCER\_CC1NP}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga0ca0aedba14241caff739afb3c3ee291}{TIM\_CCER\_CC1P}}))\ <<\ SHIFT\_TAB\_CCxP[iChannel]);}
\DoxyCodeLine{02899\ \}}
\DoxyCodeLine{02900\ }
\DoxyCodeLine{02919\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_IC\_SetActiveInput(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ Channel,\ uint32\_t\ ICActiveInput)}
\DoxyCodeLine{02920\ \{}
\DoxyCodeLine{02921\ \ \ uint8\_t\ iChannel\ =\ TIM\_GET\_CHANNEL\_INDEX(Channel);}
\DoxyCodeLine{02922\ \ \ \mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *pReg\ =\ (\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *)((uint32\_t)((uint32\_t)(\&TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a0f2291e7efdf3222689ef13e9be2ea4a}{CCMR1}})\ +\ OFFSET\_TAB\_CCMRx[iChannel]));}
\DoxyCodeLine{02923\ \ \ MODIFY\_REG(*pReg,\ ((\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga95291df1eaf532c5c996d176648938eb}{TIM\_CCMR1\_CC1S}})\ <<\ SHIFT\_TAB\_ICxx[iChannel]),\ (ICActiveInput\ >>\ 16U)\ <<\ SHIFT\_TAB\_ICxx[iChannel]);}
\DoxyCodeLine{02924\ \}}
\DoxyCodeLine{02925\ }
\DoxyCodeLine{02943\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IC\_GetActiveInput(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ Channel)}
\DoxyCodeLine{02944\ \{}
\DoxyCodeLine{02945\ \ \ uint8\_t\ iChannel\ =\ TIM\_GET\_CHANNEL\_INDEX(Channel);}
\DoxyCodeLine{02946\ \ \ \textcolor{keyword}{const}\ \mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *pReg\ =\ (\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *)((uint32\_t)((uint32\_t)(\&TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a0f2291e7efdf3222689ef13e9be2ea4a}{CCMR1}})\ +\ OFFSET\_TAB\_CCMRx[iChannel]));}
\DoxyCodeLine{02947\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(*pReg,\ ((\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga95291df1eaf532c5c996d176648938eb}{TIM\_CCMR1\_CC1S}})\ <<\ SHIFT\_TAB\_ICxx[iChannel]))\ >>\ SHIFT\_TAB\_ICxx[iChannel])\ <<\ 16U);}
\DoxyCodeLine{02948\ \}}
\DoxyCodeLine{02949\ }
\DoxyCodeLine{02969\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_IC\_SetPrescaler(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ Channel,\ uint32\_t\ ICPrescaler)}
\DoxyCodeLine{02970\ \{}
\DoxyCodeLine{02971\ \ \ uint8\_t\ iChannel\ =\ TIM\_GET\_CHANNEL\_INDEX(Channel);}
\DoxyCodeLine{02972\ \ \ \mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *pReg\ =\ (\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *)((uint32\_t)((uint32\_t)(\&TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a0f2291e7efdf3222689ef13e9be2ea4a}{CCMR1}})\ +\ OFFSET\_TAB\_CCMRx[iChannel]));}
\DoxyCodeLine{02973\ \ \ MODIFY\_REG(*pReg,\ ((\mbox{\hyperlink{group___peripheral___registers___bits___definition_gab46b7186665f5308cd2ca52acfb63e72}{TIM\_CCMR1\_IC1PSC}})\ <<\ SHIFT\_TAB\_ICxx[iChannel]),\ (ICPrescaler\ >>\ 16U)\ <<\ SHIFT\_TAB\_ICxx[iChannel]);}
\DoxyCodeLine{02974\ \}}
\DoxyCodeLine{02975\ }
\DoxyCodeLine{02994\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IC\_GetPrescaler(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ Channel)}
\DoxyCodeLine{02995\ \{}
\DoxyCodeLine{02996\ \ \ uint8\_t\ iChannel\ =\ TIM\_GET\_CHANNEL\_INDEX(Channel);}
\DoxyCodeLine{02997\ \ \ \textcolor{keyword}{const}\ \mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *pReg\ =\ (\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *)((uint32\_t)((uint32\_t)(\&TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a0f2291e7efdf3222689ef13e9be2ea4a}{CCMR1}})\ +\ OFFSET\_TAB\_CCMRx[iChannel]));}
\DoxyCodeLine{02998\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(*pReg,\ ((\mbox{\hyperlink{group___peripheral___registers___bits___definition_gab46b7186665f5308cd2ca52acfb63e72}{TIM\_CCMR1\_IC1PSC}})\ <<\ SHIFT\_TAB\_ICxx[iChannel]))\ >>\ SHIFT\_TAB\_ICxx[iChannel])\ <<\ 16U);}
\DoxyCodeLine{02999\ \}}
\DoxyCodeLine{03000\ }
\DoxyCodeLine{03032\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_IC\_SetFilter(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ Channel,\ uint32\_t\ ICFilter)}
\DoxyCodeLine{03033\ \{}
\DoxyCodeLine{03034\ \ \ uint8\_t\ iChannel\ =\ TIM\_GET\_CHANNEL\_INDEX(Channel);}
\DoxyCodeLine{03035\ \ \ \mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *pReg\ =\ (\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *)((uint32\_t)((uint32\_t)(\&TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a0f2291e7efdf3222689ef13e9be2ea4a}{CCMR1}})\ +\ OFFSET\_TAB\_CCMRx[iChannel]));}
\DoxyCodeLine{03036\ \ \ MODIFY\_REG(*pReg,\ ((\mbox{\hyperlink{group___peripheral___registers___bits___definition_gab0ee123675d8b8f98b5a6eeeccf37912}{TIM\_CCMR1\_IC1F}})\ <<\ SHIFT\_TAB\_ICxx[iChannel]),\ (ICFilter\ >>\ 16U)\ <<\ SHIFT\_TAB\_ICxx[iChannel]);}
\DoxyCodeLine{03037\ \}}
\DoxyCodeLine{03038\ }
\DoxyCodeLine{03069\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IC\_GetFilter(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ Channel)}
\DoxyCodeLine{03070\ \{}
\DoxyCodeLine{03071\ \ \ uint8\_t\ iChannel\ =\ TIM\_GET\_CHANNEL\_INDEX(Channel);}
\DoxyCodeLine{03072\ \ \ \textcolor{keyword}{const}\ \mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *pReg\ =\ (\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *)((uint32\_t)((uint32\_t)(\&TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a0f2291e7efdf3222689ef13e9be2ea4a}{CCMR1}})\ +\ OFFSET\_TAB\_CCMRx[iChannel]));}
\DoxyCodeLine{03073\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(*pReg,\ ((\mbox{\hyperlink{group___peripheral___registers___bits___definition_gab0ee123675d8b8f98b5a6eeeccf37912}{TIM\_CCMR1\_IC1F}})\ <<\ SHIFT\_TAB\_ICxx[iChannel]))\ >>\ SHIFT\_TAB\_ICxx[iChannel])\ <<\ 16U);}
\DoxyCodeLine{03074\ \}}
\DoxyCodeLine{03075\ }
\DoxyCodeLine{03098\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_IC\_SetPolarity(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ Channel,\ uint32\_t\ ICPolarity)}
\DoxyCodeLine{03099\ \{}
\DoxyCodeLine{03100\ \ \ uint8\_t\ iChannel\ =\ TIM\_GET\_CHANNEL\_INDEX(Channel);}
\DoxyCodeLine{03101\ \ \ MODIFY\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_ad7271cc1eec9ef16e4ee5401626c0b3b}{CCER}},\ ((\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga403fc501d4d8de6cabee6b07acb81a36}{TIM\_CCER\_CC1NP}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga0ca0aedba14241caff739afb3c3ee291}{TIM\_CCER\_CC1P}})\ <<\ SHIFT\_TAB\_CCxP[iChannel]),}
\DoxyCodeLine{03102\ \ \ \ \ \ \ \ \ \ \ \ \ \ ICPolarity\ <<\ SHIFT\_TAB\_CCxP[iChannel]);}
\DoxyCodeLine{03103\ \}}
\DoxyCodeLine{03104\ }
\DoxyCodeLine{03126\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IC\_GetPolarity(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ Channel)}
\DoxyCodeLine{03127\ \{}
\DoxyCodeLine{03128\ \ \ uint8\_t\ iChannel\ =\ TIM\_GET\_CHANNEL\_INDEX(Channel);}
\DoxyCodeLine{03129\ \ \ \textcolor{keywordflow}{return}\ (READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_ad7271cc1eec9ef16e4ee5401626c0b3b}{CCER}},\ ((\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga403fc501d4d8de6cabee6b07acb81a36}{TIM\_CCER\_CC1NP}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga0ca0aedba14241caff739afb3c3ee291}{TIM\_CCER\_CC1P}})\ <<\ SHIFT\_TAB\_CCxP[iChannel]))\ >>}
\DoxyCodeLine{03130\ \ \ \ \ \ \ \ \ \ \ SHIFT\_TAB\_CCxP[iChannel]);}
\DoxyCodeLine{03131\ \}}
\DoxyCodeLine{03132\ }
\DoxyCodeLine{03141\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_IC\_EnableXORCombination(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{03142\ \{}
\DoxyCodeLine{03143\ \ \ SET\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a6b1ae85138ed91686bf63699c61ef835}{CR2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gad07504497b70af628fa1aee8fe7ef63c}{TIM\_CR2\_TI1S}});}
\DoxyCodeLine{03144\ \}}
\DoxyCodeLine{03145\ }
\DoxyCodeLine{03154\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_IC\_DisableXORCombination(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{03155\ \{}
\DoxyCodeLine{03156\ \ \ CLEAR\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a6b1ae85138ed91686bf63699c61ef835}{CR2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gad07504497b70af628fa1aee8fe7ef63c}{TIM\_CR2\_TI1S}});}
\DoxyCodeLine{03157\ \}}
\DoxyCodeLine{03158\ }
\DoxyCodeLine{03167\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IC\_IsEnabledXORCombination(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{03168\ \{}
\DoxyCodeLine{03169\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a6b1ae85138ed91686bf63699c61ef835}{CR2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gad07504497b70af628fa1aee8fe7ef63c}{TIM\_CR2\_TI1S}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gad07504497b70af628fa1aee8fe7ef63c}{TIM\_CR2\_TI1S}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{03170\ \}}
\DoxyCodeLine{03171\ }
\DoxyCodeLine{03183\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IC\_GetCaptureCH1(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{03184\ \{}
\DoxyCodeLine{03185\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a0dd9c06729a5eb6179c6d0d60faca7ed}{CCR1}}));}
\DoxyCodeLine{03186\ \}}
\DoxyCodeLine{03187\ }
\DoxyCodeLine{03199\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IC\_GetCaptureCH2(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{03200\ \{}
\DoxyCodeLine{03201\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a4d1171e9a61538424b8ef1f2571986d0}{CCR2}}));}
\DoxyCodeLine{03202\ \}}
\DoxyCodeLine{03203\ }
\DoxyCodeLine{03215\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IC\_GetCaptureCH3(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{03216\ \{}
\DoxyCodeLine{03217\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_ac83441bfb8d0287080dcbd945a272a74}{CCR3}}));}
\DoxyCodeLine{03218\ \}}
\DoxyCodeLine{03219\ }
\DoxyCodeLine{03231\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IC\_GetCaptureCH4(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{03232\ \{}
\DoxyCodeLine{03233\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a5ba381c3f312fdf5e0b4119641b3b0aa}{CCR4}}));}
\DoxyCodeLine{03234\ \}}
\DoxyCodeLine{03235\ }
\DoxyCodeLine{03239\ }
\DoxyCodeLine{03252\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_EnableExternalClock(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{03253\ \{}
\DoxyCodeLine{03254\ \ \ SET\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a67d30593bcb68b98186ebe5bc8dc34b1}{SMCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga331a1d5f39d5f47b5409054e693fc651}{TIM\_SMCR\_ECE}});}
\DoxyCodeLine{03255\ \}}
\DoxyCodeLine{03256\ }
\DoxyCodeLine{03265\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_DisableExternalClock(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{03266\ \{}
\DoxyCodeLine{03267\ \ \ CLEAR\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a67d30593bcb68b98186ebe5bc8dc34b1}{SMCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga331a1d5f39d5f47b5409054e693fc651}{TIM\_SMCR\_ECE}});}
\DoxyCodeLine{03268\ \}}
\DoxyCodeLine{03269\ }
\DoxyCodeLine{03278\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IsEnabledExternalClock(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{03279\ \{}
\DoxyCodeLine{03280\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a67d30593bcb68b98186ebe5bc8dc34b1}{SMCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga331a1d5f39d5f47b5409054e693fc651}{TIM\_SMCR\_ECE}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga331a1d5f39d5f47b5409054e693fc651}{TIM\_SMCR\_ECE}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{03281\ \}}
\DoxyCodeLine{03282\ }
\DoxyCodeLine{03302\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_SetClockSource(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ ClockSource)}
\DoxyCodeLine{03303\ \{}
\DoxyCodeLine{03304\ \ \ MODIFY\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a67d30593bcb68b98186ebe5bc8dc34b1}{SMCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gae92349731a6107e0f3a251b44a67c7ea}{TIM\_SMCR\_SMS}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga331a1d5f39d5f47b5409054e693fc651}{TIM\_SMCR\_ECE}},\ ClockSource);}
\DoxyCodeLine{03305\ \}}
\DoxyCodeLine{03306\ }
\DoxyCodeLine{03319\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_SetEncoderMode(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ EncoderMode)}
\DoxyCodeLine{03320\ \{}
\DoxyCodeLine{03321\ \ \ MODIFY\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a67d30593bcb68b98186ebe5bc8dc34b1}{SMCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gae92349731a6107e0f3a251b44a67c7ea}{TIM\_SMCR\_SMS}},\ EncoderMode);}
\DoxyCodeLine{03322\ \}}
\DoxyCodeLine{03323\ }
\DoxyCodeLine{03327\ }
\DoxyCodeLine{03348\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_SetTriggerOutput(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ TimerSynchronization)}
\DoxyCodeLine{03349\ \{}
\DoxyCodeLine{03350\ \ \ MODIFY\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a6b1ae85138ed91686bf63699c61ef835}{CR2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaaa6987d980e5c4c71c7d0faa1eb97a45}{TIM\_CR2\_MMS}},\ TimerSynchronization);}
\DoxyCodeLine{03351\ \}}
\DoxyCodeLine{03352\ }
\DoxyCodeLine{03378\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_SetTriggerOutput2(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ ADCSynchronization)}
\DoxyCodeLine{03379\ \{}
\DoxyCodeLine{03380\ \ \ MODIFY\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a6b1ae85138ed91686bf63699c61ef835}{CR2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gae199132077792fb8efa01b87edd1c033}{TIM\_CR2\_MMS2}},\ ADCSynchronization);}
\DoxyCodeLine{03381\ \}}
\DoxyCodeLine{03382\ }
\DoxyCodeLine{03397\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_SetSlaveMode(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ SlaveMode)}
\DoxyCodeLine{03398\ \{}
\DoxyCodeLine{03399\ \ \ MODIFY\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a67d30593bcb68b98186ebe5bc8dc34b1}{SMCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gae92349731a6107e0f3a251b44a67c7ea}{TIM\_SMCR\_SMS}},\ SlaveMode);}
\DoxyCodeLine{03400\ \}}
\DoxyCodeLine{03401\ }
\DoxyCodeLine{03431\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_SetTriggerInput(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ TriggerInput)}
\DoxyCodeLine{03432\ \{}
\DoxyCodeLine{03433\ \ \ MODIFY\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a67d30593bcb68b98186ebe5bc8dc34b1}{SMCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga8680e719bca2b672d850504220ae51fc}{TIM\_SMCR\_TS}},\ TriggerInput);}
\DoxyCodeLine{03434\ \}}
\DoxyCodeLine{03435\ }
\DoxyCodeLine{03444\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_EnableMasterSlaveMode(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{03445\ \{}
\DoxyCodeLine{03446\ \ \ SET\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a67d30593bcb68b98186ebe5bc8dc34b1}{SMCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga52101db4ca2c7b3003f1b16a49b2032c}{TIM\_SMCR\_MSM}});}
\DoxyCodeLine{03447\ \}}
\DoxyCodeLine{03448\ }
\DoxyCodeLine{03457\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_DisableMasterSlaveMode(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{03458\ \{}
\DoxyCodeLine{03459\ \ \ CLEAR\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a67d30593bcb68b98186ebe5bc8dc34b1}{SMCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga52101db4ca2c7b3003f1b16a49b2032c}{TIM\_SMCR\_MSM}});}
\DoxyCodeLine{03460\ \}}
\DoxyCodeLine{03461\ }
\DoxyCodeLine{03470\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IsEnabledMasterSlaveMode(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{03471\ \{}
\DoxyCodeLine{03472\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a67d30593bcb68b98186ebe5bc8dc34b1}{SMCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga52101db4ca2c7b3003f1b16a49b2032c}{TIM\_SMCR\_MSM}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga52101db4ca2c7b3003f1b16a49b2032c}{TIM\_SMCR\_MSM}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{03473\ \}}
\DoxyCodeLine{03474\ }
\DoxyCodeLine{03510\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_ConfigETR(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ ETRPolarity,\ uint32\_t\ ETRPrescaler,}
\DoxyCodeLine{03511\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ uint32\_t\ ETRFilter)}
\DoxyCodeLine{03512\ \{}
\DoxyCodeLine{03513\ \ \ MODIFY\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a67d30593bcb68b98186ebe5bc8dc34b1}{SMCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga2a5f335c3d7a4f82d1e91dc1511e3322}{TIM\_SMCR\_ETP}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga0ebb9e631876435e276211d88e797386}{TIM\_SMCR\_ETPS}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gae2ed8b32d9eb8eea251bd1dac4f34668}{TIM\_SMCR\_ETF}},\ ETRPolarity\ |\ ETRPrescaler\ |\ ETRFilter);}
\DoxyCodeLine{03514\ \}}
\DoxyCodeLine{03515\ }
\DoxyCodeLine{03579\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_SetETRSource(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ ETRSource)}
\DoxyCodeLine{03580\ \{}
\DoxyCodeLine{03581\ \ \ MODIFY\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a7a81e7aac9bef80b126097f8e9f36d07}{AF1}},\ TIMx\_AF1\_ETRSEL,\ ETRSource);}
\DoxyCodeLine{03582\ \}}
\DoxyCodeLine{03583\ }
\DoxyCodeLine{03587\ }
\DoxyCodeLine{03599\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_EnableBRK(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{03600\ \{}
\DoxyCodeLine{03601\ \ \ SET\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a137d3523b60951eca1e4130257b2b23d}{BDTR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga74250b040dd9fd9c09dcc54cdd6d86d8}{TIM\_BDTR\_BKE}});}
\DoxyCodeLine{03602\ \}}
\DoxyCodeLine{03603\ }
\DoxyCodeLine{03612\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_DisableBRK(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{03613\ \{}
\DoxyCodeLine{03614\ \ \ CLEAR\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a137d3523b60951eca1e4130257b2b23d}{BDTR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga74250b040dd9fd9c09dcc54cdd6d86d8}{TIM\_BDTR\_BKE}});}
\DoxyCodeLine{03615\ \}}
\DoxyCodeLine{03616\ }
\DoxyCodeLine{03617\ \textcolor{preprocessor}{\#if\ defined(TIM\_BDTR\_BKBID)}\textcolor{preprocessor}{}}
\DoxyCodeLine{03660\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_ConfigBRK(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ BreakPolarity,\ uint32\_t\ BreakFilter,}
\DoxyCodeLine{03661\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ uint32\_t\ BreakAFMode)}
\DoxyCodeLine{03662\ \{}
\DoxyCodeLine{03663\ \ \ MODIFY\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a137d3523b60951eca1e4130257b2b23d}{BDTR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga3247abbbf0d00260be051d176d88020e}{TIM\_BDTR\_BKP}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gae2be17c432a12ce3ec4a79aa380a01b6}{TIM\_BDTR\_BKF}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga58c65231de95b67cb2d115064ab57f60}{TIM\_BDTR\_BKBID}},\ BreakPolarity\ |\ BreakFilter\ |\ BreakAFMode);}
\DoxyCodeLine{03664\ \}}
\DoxyCodeLine{03665\ }
\DoxyCodeLine{03666\ \textcolor{preprocessor}{\#else}\textcolor{preprocessor}{}}
\DoxyCodeLine{03696\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_ConfigBRK(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ BreakPolarity,}
\DoxyCodeLine{03697\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ uint32\_t\ BreakFilter)}
\DoxyCodeLine{03698\ \{}
\DoxyCodeLine{03699\ \ \ MODIFY\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a137d3523b60951eca1e4130257b2b23d}{BDTR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga3247abbbf0d00260be051d176d88020e}{TIM\_BDTR\_BKP}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gae2be17c432a12ce3ec4a79aa380a01b6}{TIM\_BDTR\_BKF}},\ BreakPolarity\ |\ BreakFilter);}
\DoxyCodeLine{03700\ \}}
\DoxyCodeLine{03701\ }
\DoxyCodeLine{03702\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ TIM\_BDTR\_BKBID\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{03703\ \textcolor{preprocessor}{\#if\ defined(TIM\_BDTR\_BKBID)}\textcolor{preprocessor}{}}
\DoxyCodeLine{03714\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_DisarmBRK(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{03715\ \{}
\DoxyCodeLine{03716\ \ \ SET\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a137d3523b60951eca1e4130257b2b23d}{BDTR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga2ed336e59081fe830617f97dcb71678b}{TIM\_BDTR\_BKDSRM}});}
\DoxyCodeLine{03717\ \}}
\DoxyCodeLine{03718\ }
\DoxyCodeLine{03719\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*TIM\_BDTR\_BKBID\ */}\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{03728\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_EnableBRK2(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{03729\ \{}
\DoxyCodeLine{03730\ \ \ SET\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a137d3523b60951eca1e4130257b2b23d}{BDTR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga50aff10d1577a94de8c4aa46cd2cbdb5}{TIM\_BDTR\_BK2E}});}
\DoxyCodeLine{03731\ \}}
\DoxyCodeLine{03732\ }
\DoxyCodeLine{03741\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_DisableBRK2(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{03742\ \{}
\DoxyCodeLine{03743\ \ \ CLEAR\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a137d3523b60951eca1e4130257b2b23d}{BDTR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga50aff10d1577a94de8c4aa46cd2cbdb5}{TIM\_BDTR\_BK2E}});}
\DoxyCodeLine{03744\ \}}
\DoxyCodeLine{03745\ }
\DoxyCodeLine{03746\ \textcolor{preprocessor}{\#if\ defined(TIM\_BDTR\_BKBID)}\textcolor{preprocessor}{}}
\DoxyCodeLine{03789\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_ConfigBRK2(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ Break2Polarity,\ uint32\_t\ Break2Filter,}
\DoxyCodeLine{03790\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ uint32\_t\ Break2AFMode)}
\DoxyCodeLine{03791\ \{}
\DoxyCodeLine{03792\ \ \ MODIFY\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a137d3523b60951eca1e4130257b2b23d}{BDTR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga94911ade52aef76f5ad41613f9fc9590}{TIM\_BDTR\_BK2P}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gacb338853d60dffd23d45fc67b6649705}{TIM\_BDTR\_BK2F}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gab3c8126b8cc13f3338b59f1e91202d43}{TIM\_BDTR\_BK2BID}},\ Break2Polarity\ |\ Break2Filter\ |\ Break2AFMode);}
\DoxyCodeLine{03793\ \}}
\DoxyCodeLine{03794\ }
\DoxyCodeLine{03795\ \textcolor{preprocessor}{\#else}\textcolor{preprocessor}{}}
\DoxyCodeLine{03825\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_ConfigBRK2(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ Break2Polarity,\ uint32\_t\ Break2Filter)}
\DoxyCodeLine{03826\ \{}
\DoxyCodeLine{03827\ \ \ MODIFY\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a137d3523b60951eca1e4130257b2b23d}{BDTR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga94911ade52aef76f5ad41613f9fc9590}{TIM\_BDTR\_BK2P}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gacb338853d60dffd23d45fc67b6649705}{TIM\_BDTR\_BK2F}},\ Break2Polarity\ |\ Break2Filter);}
\DoxyCodeLine{03828\ \}}
\DoxyCodeLine{03829\ }
\DoxyCodeLine{03830\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*TIM\_BDTR\_BKBID\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{03831\ \textcolor{preprocessor}{\#if\ defined(TIM\_BDTR\_BKBID)}\textcolor{preprocessor}{}}
\DoxyCodeLine{03842\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_DisarmBRK2(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{03843\ \{}
\DoxyCodeLine{03844\ \ \ SET\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a137d3523b60951eca1e4130257b2b23d}{BDTR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga759883f669298c750d8dbf3d2fd2fab2}{TIM\_BDTR\_BK2DSRM}});}
\DoxyCodeLine{03845\ \}}
\DoxyCodeLine{03846\ }
\DoxyCodeLine{03847\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*TIM\_BDTR\_BKBID\ */}\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{03863\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_SetOffStates(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ OffStateIdle,\ uint32\_t\ OffStateRun)}
\DoxyCodeLine{03864\ \{}
\DoxyCodeLine{03865\ \ \ MODIFY\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a137d3523b60951eca1e4130257b2b23d}{BDTR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gab1cf04e70ccf3d4aba5afcf2496a411a}{TIM\_BDTR\_OSSI}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf9435f36d53c6be1107e57ab6a82c16e}{TIM\_BDTR\_OSSR}},\ OffStateIdle\ |\ OffStateRun);}
\DoxyCodeLine{03866\ \}}
\DoxyCodeLine{03867\ }
\DoxyCodeLine{03876\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_EnableAutomaticOutput(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{03877\ \{}
\DoxyCodeLine{03878\ \ \ SET\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a137d3523b60951eca1e4130257b2b23d}{BDTR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga59f15008050f91fa3ecc9eaaa971a509}{TIM\_BDTR\_AOE}});}
\DoxyCodeLine{03879\ \}}
\DoxyCodeLine{03880\ }
\DoxyCodeLine{03889\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_DisableAutomaticOutput(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{03890\ \{}
\DoxyCodeLine{03891\ \ \ CLEAR\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a137d3523b60951eca1e4130257b2b23d}{BDTR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga59f15008050f91fa3ecc9eaaa971a509}{TIM\_BDTR\_AOE}});}
\DoxyCodeLine{03892\ \}}
\DoxyCodeLine{03893\ }
\DoxyCodeLine{03902\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IsEnabledAutomaticOutput(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{03903\ \{}
\DoxyCodeLine{03904\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a137d3523b60951eca1e4130257b2b23d}{BDTR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga59f15008050f91fa3ecc9eaaa971a509}{TIM\_BDTR\_AOE}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga59f15008050f91fa3ecc9eaaa971a509}{TIM\_BDTR\_AOE}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{03905\ \}}
\DoxyCodeLine{03906\ }
\DoxyCodeLine{03917\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_EnableAllOutputs(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{03918\ \{}
\DoxyCodeLine{03919\ \ \ SET\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a137d3523b60951eca1e4130257b2b23d}{BDTR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga277a096614829feba2d0a4fbb7d3dffc}{TIM\_BDTR\_MOE}});}
\DoxyCodeLine{03920\ \}}
\DoxyCodeLine{03921\ }
\DoxyCodeLine{03932\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_DisableAllOutputs(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{03933\ \{}
\DoxyCodeLine{03934\ \ \ CLEAR\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a137d3523b60951eca1e4130257b2b23d}{BDTR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga277a096614829feba2d0a4fbb7d3dffc}{TIM\_BDTR\_MOE}});}
\DoxyCodeLine{03935\ \}}
\DoxyCodeLine{03936\ }
\DoxyCodeLine{03945\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IsEnabledAllOutputs(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{03946\ \{}
\DoxyCodeLine{03947\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a137d3523b60951eca1e4130257b2b23d}{BDTR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga277a096614829feba2d0a4fbb7d3dffc}{TIM\_BDTR\_MOE}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga277a096614829feba2d0a4fbb7d3dffc}{TIM\_BDTR\_MOE}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{03948\ \}}
\DoxyCodeLine{03949\ }
\DoxyCodeLine{03950\ \textcolor{preprocessor}{\#if\ defined(TIM\_BREAK\_INPUT\_SUPPORT)}\textcolor{preprocessor}{}}
\DoxyCodeLine{03974\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_EnableBreakInputSource(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ BreakInput,\ uint32\_t\ Source)}
\DoxyCodeLine{03975\ \{}
\DoxyCodeLine{03976\ \ \ \mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *pReg\ =\ (\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *)((uint32\_t)((uint32\_t)(\&TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a7a81e7aac9bef80b126097f8e9f36d07}{AF1}})\ +\ BreakInput));}
\DoxyCodeLine{03977\ \ \ SET\_BIT(*pReg,\ Source);}
\DoxyCodeLine{03978\ \}}
\DoxyCodeLine{03979\ }
\DoxyCodeLine{04003\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_DisableBreakInputSource(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ BreakInput,\ uint32\_t\ Source)}
\DoxyCodeLine{04004\ \{}
\DoxyCodeLine{04005\ \ \ \mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *pReg\ =\ (\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *)((uint32\_t)((uint32\_t)(\&TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a7a81e7aac9bef80b126097f8e9f36d07}{AF1}})\ +\ BreakInput));}
\DoxyCodeLine{04006\ \ \ CLEAR\_BIT(*pReg,\ Source);}
\DoxyCodeLine{04007\ \}}
\DoxyCodeLine{04008\ }
\DoxyCodeLine{04032\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_SetBreakInputSourcePolarity(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ BreakInput,\ uint32\_t\ Source,}
\DoxyCodeLine{04033\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ uint32\_t\ Polarity)}
\DoxyCodeLine{04034\ \{}
\DoxyCodeLine{04035\ \ \ \mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *pReg\ =\ (\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *)((uint32\_t)((uint32\_t)(\&TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a7a81e7aac9bef80b126097f8e9f36d07}{AF1}})\ +\ BreakInput));}
\DoxyCodeLine{04036\ \ \ MODIFY\_REG(*pReg,\ (TIMx\_AF1\_BKINP\ <<\ TIM\_POSITION\_BRK\_SOURCE),\ (Polarity\ <<\ TIM\_POSITION\_BRK\_SOURCE));}
\DoxyCodeLine{04037\ \}}
\DoxyCodeLine{04038\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ TIM\_BREAK\_INPUT\_SUPPORT\ */}\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{04042\ }
\DoxyCodeLine{04100\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_ConfigDMABurst(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ DMABurstBaseAddress,\ uint32\_t\ DMABurstLength)}
\DoxyCodeLine{04101\ \{}
\DoxyCodeLine{04102\ \ \ MODIFY\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a7efe9ea8067044cac449ada756ebc2d1}{DCR}},\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gab9e197a78484567d4c6093c28265f3eb}{TIM\_DCR\_DBL}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gabf9051ecac123cd89f9d2a835e4cde2e}{TIM\_DCR\_DBA}}),\ (DMABurstBaseAddress\ |\ DMABurstLength));}
\DoxyCodeLine{04103\ \}}
\DoxyCodeLine{04104\ }
\DoxyCodeLine{04108\ }
\DoxyCodeLine{04185\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_SetRemap(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ Remap)}
\DoxyCodeLine{04186\ \{}
\DoxyCodeLine{04187\ \ \ MODIFY\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a48ce9972eb643ae4f34bd75a0b931ad4}{TISEL}},\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga5168e7f269c569c733b656bb86b5c3a5}{TIM\_TISEL\_TI1SEL}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaff4d8ae0f229b42960fe34be62a3b499}{TIM\_TISEL\_TI2SEL}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga7c19a6840ec57afc1b9ae48703f60fc1}{TIM\_TISEL\_TI3SEL}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga7eff9d6247daaa7bdbd6f009ab80d595}{TIM\_TISEL\_TI4SEL}}),\ Remap);}
\DoxyCodeLine{04188\ \}}
\DoxyCodeLine{04189\ }
\DoxyCodeLine{04193\ }
\DoxyCodeLine{04203\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_ClearFlag\_UPDATE(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04204\ \{}
\DoxyCodeLine{04205\ \ \ WRITE\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_acedfc978c879835c05ef1788ad26b2ff}{SR}},\ \string~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_gac8c03fabc10654d2a3f76ea40fcdbde6}{TIM\_SR\_UIF}}));}
\DoxyCodeLine{04206\ \}}
\DoxyCodeLine{04207\ }
\DoxyCodeLine{04214\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IsActiveFlag\_UPDATE(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04215\ \{}
\DoxyCodeLine{04216\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_acedfc978c879835c05ef1788ad26b2ff}{SR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gac8c03fabc10654d2a3f76ea40fcdbde6}{TIM\_SR\_UIF}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gac8c03fabc10654d2a3f76ea40fcdbde6}{TIM\_SR\_UIF}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{04217\ \}}
\DoxyCodeLine{04218\ }
\DoxyCodeLine{04225\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_ClearFlag\_CC1(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04226\ \{}
\DoxyCodeLine{04227\ \ \ WRITE\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_acedfc978c879835c05ef1788ad26b2ff}{SR}},\ \string~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga449a61344a97608d85384c29f003c0e9}{TIM\_SR\_CC1IF}}));}
\DoxyCodeLine{04228\ \}}
\DoxyCodeLine{04229\ }
\DoxyCodeLine{04236\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IsActiveFlag\_CC1(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04237\ \{}
\DoxyCodeLine{04238\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_acedfc978c879835c05ef1788ad26b2ff}{SR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga449a61344a97608d85384c29f003c0e9}{TIM\_SR\_CC1IF}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga449a61344a97608d85384c29f003c0e9}{TIM\_SR\_CC1IF}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{04239\ \}}
\DoxyCodeLine{04240\ }
\DoxyCodeLine{04247\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_ClearFlag\_CC2(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04248\ \{}
\DoxyCodeLine{04249\ \ \ WRITE\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_acedfc978c879835c05ef1788ad26b2ff}{SR}},\ \string~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga25a48bf099467169aa50464fbf462bd8}{TIM\_SR\_CC2IF}}));}
\DoxyCodeLine{04250\ \}}
\DoxyCodeLine{04251\ }
\DoxyCodeLine{04258\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IsActiveFlag\_CC2(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04259\ \{}
\DoxyCodeLine{04260\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_acedfc978c879835c05ef1788ad26b2ff}{SR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga25a48bf099467169aa50464fbf462bd8}{TIM\_SR\_CC2IF}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga25a48bf099467169aa50464fbf462bd8}{TIM\_SR\_CC2IF}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{04261\ \}}
\DoxyCodeLine{04262\ }
\DoxyCodeLine{04269\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_ClearFlag\_CC3(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04270\ \{}
\DoxyCodeLine{04271\ \ \ WRITE\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_acedfc978c879835c05ef1788ad26b2ff}{SR}},\ \string~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_gad3cf234a1059c0a04799e88382cdc0f2}{TIM\_SR\_CC3IF}}));}
\DoxyCodeLine{04272\ \}}
\DoxyCodeLine{04273\ }
\DoxyCodeLine{04280\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IsActiveFlag\_CC3(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04281\ \{}
\DoxyCodeLine{04282\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_acedfc978c879835c05ef1788ad26b2ff}{SR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gad3cf234a1059c0a04799e88382cdc0f2}{TIM\_SR\_CC3IF}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gad3cf234a1059c0a04799e88382cdc0f2}{TIM\_SR\_CC3IF}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{04283\ \}}
\DoxyCodeLine{04284\ }
\DoxyCodeLine{04291\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_ClearFlag\_CC4(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04292\ \{}
\DoxyCodeLine{04293\ \ \ WRITE\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_acedfc978c879835c05ef1788ad26b2ff}{SR}},\ \string~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_gacade8a06303bf216bfb03140c7e16cac}{TIM\_SR\_CC4IF}}));}
\DoxyCodeLine{04294\ \}}
\DoxyCodeLine{04295\ }
\DoxyCodeLine{04302\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IsActiveFlag\_CC4(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04303\ \{}
\DoxyCodeLine{04304\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_acedfc978c879835c05ef1788ad26b2ff}{SR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gacade8a06303bf216bfb03140c7e16cac}{TIM\_SR\_CC4IF}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gacade8a06303bf216bfb03140c7e16cac}{TIM\_SR\_CC4IF}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{04305\ \}}
\DoxyCodeLine{04306\ }
\DoxyCodeLine{04313\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_ClearFlag\_CC5(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04314\ \{}
\DoxyCodeLine{04315\ \ \ WRITE\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_acedfc978c879835c05ef1788ad26b2ff}{SR}},\ \string~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga2167773377ba03c863cc49342c67789f}{TIM\_SR\_CC5IF}}));}
\DoxyCodeLine{04316\ \}}
\DoxyCodeLine{04317\ }
\DoxyCodeLine{04324\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IsActiveFlag\_CC5(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04325\ \{}
\DoxyCodeLine{04326\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_acedfc978c879835c05ef1788ad26b2ff}{SR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga2167773377ba03c863cc49342c67789f}{TIM\_SR\_CC5IF}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga2167773377ba03c863cc49342c67789f}{TIM\_SR\_CC5IF}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{04327\ \}}
\DoxyCodeLine{04328\ }
\DoxyCodeLine{04335\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_ClearFlag\_CC6(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04336\ \{}
\DoxyCodeLine{04337\ \ \ WRITE\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_acedfc978c879835c05ef1788ad26b2ff}{SR}},\ \string~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_gad16e2f81b0c4fe28e323f3302c2240db}{TIM\_SR\_CC6IF}}));}
\DoxyCodeLine{04338\ \}}
\DoxyCodeLine{04339\ }
\DoxyCodeLine{04346\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IsActiveFlag\_CC6(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04347\ \{}
\DoxyCodeLine{04348\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_acedfc978c879835c05ef1788ad26b2ff}{SR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gad16e2f81b0c4fe28e323f3302c2240db}{TIM\_SR\_CC6IF}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gad16e2f81b0c4fe28e323f3302c2240db}{TIM\_SR\_CC6IF}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{04349\ \}}
\DoxyCodeLine{04350\ }
\DoxyCodeLine{04357\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_ClearFlag\_COM(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04358\ \{}
\DoxyCodeLine{04359\ \ \ WRITE\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_acedfc978c879835c05ef1788ad26b2ff}{SR}},\ \string~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga91775c029171c4585e9cca6ebf1cd57a}{TIM\_SR\_COMIF}}));}
\DoxyCodeLine{04360\ \}}
\DoxyCodeLine{04361\ }
\DoxyCodeLine{04368\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IsActiveFlag\_COM(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04369\ \{}
\DoxyCodeLine{04370\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_acedfc978c879835c05ef1788ad26b2ff}{SR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga91775c029171c4585e9cca6ebf1cd57a}{TIM\_SR\_COMIF}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga91775c029171c4585e9cca6ebf1cd57a}{TIM\_SR\_COMIF}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{04371\ \}}
\DoxyCodeLine{04372\ }
\DoxyCodeLine{04379\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_ClearFlag\_TRIG(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04380\ \{}
\DoxyCodeLine{04381\ \ \ WRITE\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_acedfc978c879835c05ef1788ad26b2ff}{SR}},\ \string~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga7c8b16f3ced6ec03e9001276b134846e}{TIM\_SR\_TIF}}));}
\DoxyCodeLine{04382\ \}}
\DoxyCodeLine{04383\ }
\DoxyCodeLine{04390\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IsActiveFlag\_TRIG(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04391\ \{}
\DoxyCodeLine{04392\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_acedfc978c879835c05ef1788ad26b2ff}{SR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga7c8b16f3ced6ec03e9001276b134846e}{TIM\_SR\_TIF}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga7c8b16f3ced6ec03e9001276b134846e}{TIM\_SR\_TIF}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{04393\ \}}
\DoxyCodeLine{04394\ }
\DoxyCodeLine{04401\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_ClearFlag\_BRK(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04402\ \{}
\DoxyCodeLine{04403\ \ \ WRITE\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_acedfc978c879835c05ef1788ad26b2ff}{SR}},\ \string~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6d52cd5a57c9a26b0d993c93d9875097}{TIM\_SR\_BIF}}));}
\DoxyCodeLine{04404\ \}}
\DoxyCodeLine{04405\ }
\DoxyCodeLine{04412\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IsActiveFlag\_BRK(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04413\ \{}
\DoxyCodeLine{04414\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_acedfc978c879835c05ef1788ad26b2ff}{SR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6d52cd5a57c9a26b0d993c93d9875097}{TIM\_SR\_BIF}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6d52cd5a57c9a26b0d993c93d9875097}{TIM\_SR\_BIF}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{04415\ \}}
\DoxyCodeLine{04416\ }
\DoxyCodeLine{04423\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_ClearFlag\_BRK2(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04424\ \{}
\DoxyCodeLine{04425\ \ \ WRITE\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_acedfc978c879835c05ef1788ad26b2ff}{SR}},\ \string~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaef0c136d9338baf71a64ff650b385645}{TIM\_SR\_B2IF}}));}
\DoxyCodeLine{04426\ \}}
\DoxyCodeLine{04427\ }
\DoxyCodeLine{04434\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IsActiveFlag\_BRK2(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04435\ \{}
\DoxyCodeLine{04436\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_acedfc978c879835c05ef1788ad26b2ff}{SR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaef0c136d9338baf71a64ff650b385645}{TIM\_SR\_B2IF}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaef0c136d9338baf71a64ff650b385645}{TIM\_SR\_B2IF}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{04437\ \}}
\DoxyCodeLine{04438\ }
\DoxyCodeLine{04445\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_ClearFlag\_CC1OVR(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04446\ \{}
\DoxyCodeLine{04447\ \ \ WRITE\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_acedfc978c879835c05ef1788ad26b2ff}{SR}},\ \string~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga819c4b27f8fa99b537c4407521f9780c}{TIM\_SR\_CC1OF}}));}
\DoxyCodeLine{04448\ \}}
\DoxyCodeLine{04449\ }
\DoxyCodeLine{04457\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IsActiveFlag\_CC1OVR(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04458\ \{}
\DoxyCodeLine{04459\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_acedfc978c879835c05ef1788ad26b2ff}{SR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga819c4b27f8fa99b537c4407521f9780c}{TIM\_SR\_CC1OF}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga819c4b27f8fa99b537c4407521f9780c}{TIM\_SR\_CC1OF}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{04460\ \}}
\DoxyCodeLine{04461\ }
\DoxyCodeLine{04468\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_ClearFlag\_CC2OVR(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04469\ \{}
\DoxyCodeLine{04470\ \ \ WRITE\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_acedfc978c879835c05ef1788ad26b2ff}{SR}},\ \string~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga3b7798da5863d559ea9a642af6658050}{TIM\_SR\_CC2OF}}));}
\DoxyCodeLine{04471\ \}}
\DoxyCodeLine{04472\ }
\DoxyCodeLine{04480\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IsActiveFlag\_CC2OVR(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04481\ \{}
\DoxyCodeLine{04482\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_acedfc978c879835c05ef1788ad26b2ff}{SR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga3b7798da5863d559ea9a642af6658050}{TIM\_SR\_CC2OF}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga3b7798da5863d559ea9a642af6658050}{TIM\_SR\_CC2OF}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{04483\ \}}
\DoxyCodeLine{04484\ }
\DoxyCodeLine{04491\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_ClearFlag\_CC3OVR(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04492\ \{}
\DoxyCodeLine{04493\ \ \ WRITE\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_acedfc978c879835c05ef1788ad26b2ff}{SR}},\ \string~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf7a2d4c831eb641ba082156e41d03358}{TIM\_SR\_CC3OF}}));}
\DoxyCodeLine{04494\ \}}
\DoxyCodeLine{04495\ }
\DoxyCodeLine{04503\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IsActiveFlag\_CC3OVR(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04504\ \{}
\DoxyCodeLine{04505\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_acedfc978c879835c05ef1788ad26b2ff}{SR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf7a2d4c831eb641ba082156e41d03358}{TIM\_SR\_CC3OF}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf7a2d4c831eb641ba082156e41d03358}{TIM\_SR\_CC3OF}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{04506\ \}}
\DoxyCodeLine{04507\ }
\DoxyCodeLine{04514\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_ClearFlag\_CC4OVR(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04515\ \{}
\DoxyCodeLine{04516\ \ \ WRITE\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_acedfc978c879835c05ef1788ad26b2ff}{SR}},\ \string~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga81ba979e8309b66808e06e4de34bc740}{TIM\_SR\_CC4OF}}));}
\DoxyCodeLine{04517\ \}}
\DoxyCodeLine{04518\ }
\DoxyCodeLine{04526\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IsActiveFlag\_CC4OVR(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04527\ \{}
\DoxyCodeLine{04528\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_acedfc978c879835c05ef1788ad26b2ff}{SR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga81ba979e8309b66808e06e4de34bc740}{TIM\_SR\_CC4OF}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga81ba979e8309b66808e06e4de34bc740}{TIM\_SR\_CC4OF}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{04529\ \}}
\DoxyCodeLine{04530\ }
\DoxyCodeLine{04537\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_ClearFlag\_SYSBRK(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04538\ \{}
\DoxyCodeLine{04539\ \ \ WRITE\_REG(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_acedfc978c879835c05ef1788ad26b2ff}{SR}},\ \string~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_gae6c84655ac31844ff644f796ef638e06}{TIM\_SR\_SBIF}}));}
\DoxyCodeLine{04540\ \}}
\DoxyCodeLine{04541\ }
\DoxyCodeLine{04548\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IsActiveFlag\_SYSBRK(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04549\ \{}
\DoxyCodeLine{04550\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_acedfc978c879835c05ef1788ad26b2ff}{SR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gae6c84655ac31844ff644f796ef638e06}{TIM\_SR\_SBIF}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gae6c84655ac31844ff644f796ef638e06}{TIM\_SR\_SBIF}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{04551\ \}}
\DoxyCodeLine{04552\ }
\DoxyCodeLine{04556\ }
\DoxyCodeLine{04566\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_EnableIT\_UPDATE(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04567\ \{}
\DoxyCodeLine{04568\ \ \ SET\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga5c6d3e0495e6c06da4bdd0ad8995a32b}{TIM\_DIER\_UIE}});}
\DoxyCodeLine{04569\ \}}
\DoxyCodeLine{04570\ }
\DoxyCodeLine{04577\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_DisableIT\_UPDATE(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04578\ \{}
\DoxyCodeLine{04579\ \ \ CLEAR\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga5c6d3e0495e6c06da4bdd0ad8995a32b}{TIM\_DIER\_UIE}});}
\DoxyCodeLine{04580\ \}}
\DoxyCodeLine{04581\ }
\DoxyCodeLine{04588\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IsEnabledIT\_UPDATE(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04589\ \{}
\DoxyCodeLine{04590\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga5c6d3e0495e6c06da4bdd0ad8995a32b}{TIM\_DIER\_UIE}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga5c6d3e0495e6c06da4bdd0ad8995a32b}{TIM\_DIER\_UIE}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{04591\ \}}
\DoxyCodeLine{04592\ }
\DoxyCodeLine{04599\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_EnableIT\_CC1(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04600\ \{}
\DoxyCodeLine{04601\ \ \ SET\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga1ba7f7ca97eeaf6cc23cd6765c6bf678}{TIM\_DIER\_CC1IE}});}
\DoxyCodeLine{04602\ \}}
\DoxyCodeLine{04603\ }
\DoxyCodeLine{04610\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_DisableIT\_CC1(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04611\ \{}
\DoxyCodeLine{04612\ \ \ CLEAR\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga1ba7f7ca97eeaf6cc23cd6765c6bf678}{TIM\_DIER\_CC1IE}});}
\DoxyCodeLine{04613\ \}}
\DoxyCodeLine{04614\ }
\DoxyCodeLine{04621\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IsEnabledIT\_CC1(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04622\ \{}
\DoxyCodeLine{04623\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga1ba7f7ca97eeaf6cc23cd6765c6bf678}{TIM\_DIER\_CC1IE}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga1ba7f7ca97eeaf6cc23cd6765c6bf678}{TIM\_DIER\_CC1IE}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{04624\ \}}
\DoxyCodeLine{04625\ }
\DoxyCodeLine{04632\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_EnableIT\_CC2(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04633\ \{}
\DoxyCodeLine{04634\ \ \ SET\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga757c59b690770adebf33e20d3d9dec15}{TIM\_DIER\_CC2IE}});}
\DoxyCodeLine{04635\ \}}
\DoxyCodeLine{04636\ }
\DoxyCodeLine{04643\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_DisableIT\_CC2(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04644\ \{}
\DoxyCodeLine{04645\ \ \ CLEAR\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga757c59b690770adebf33e20d3d9dec15}{TIM\_DIER\_CC2IE}});}
\DoxyCodeLine{04646\ \}}
\DoxyCodeLine{04647\ }
\DoxyCodeLine{04654\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IsEnabledIT\_CC2(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04655\ \{}
\DoxyCodeLine{04656\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga757c59b690770adebf33e20d3d9dec15}{TIM\_DIER\_CC2IE}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga757c59b690770adebf33e20d3d9dec15}{TIM\_DIER\_CC2IE}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{04657\ \}}
\DoxyCodeLine{04658\ }
\DoxyCodeLine{04665\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_EnableIT\_CC3(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04666\ \{}
\DoxyCodeLine{04667\ \ \ SET\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga4edf003f04bcf250bddf5ed284201c2e}{TIM\_DIER\_CC3IE}});}
\DoxyCodeLine{04668\ \}}
\DoxyCodeLine{04669\ }
\DoxyCodeLine{04676\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_DisableIT\_CC3(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04677\ \{}
\DoxyCodeLine{04678\ \ \ CLEAR\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga4edf003f04bcf250bddf5ed284201c2e}{TIM\_DIER\_CC3IE}});}
\DoxyCodeLine{04679\ \}}
\DoxyCodeLine{04680\ }
\DoxyCodeLine{04687\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IsEnabledIT\_CC3(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04688\ \{}
\DoxyCodeLine{04689\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga4edf003f04bcf250bddf5ed284201c2e}{TIM\_DIER\_CC3IE}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga4edf003f04bcf250bddf5ed284201c2e}{TIM\_DIER\_CC3IE}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{04690\ \}}
\DoxyCodeLine{04691\ }
\DoxyCodeLine{04698\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_EnableIT\_CC4(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04699\ \{}
\DoxyCodeLine{04700\ \ \ SET\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6ad0f562a014572793b49fe87184338b}{TIM\_DIER\_CC4IE}});}
\DoxyCodeLine{04701\ \}}
\DoxyCodeLine{04702\ }
\DoxyCodeLine{04709\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_DisableIT\_CC4(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04710\ \{}
\DoxyCodeLine{04711\ \ \ CLEAR\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6ad0f562a014572793b49fe87184338b}{TIM\_DIER\_CC4IE}});}
\DoxyCodeLine{04712\ \}}
\DoxyCodeLine{04713\ }
\DoxyCodeLine{04720\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IsEnabledIT\_CC4(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04721\ \{}
\DoxyCodeLine{04722\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6ad0f562a014572793b49fe87184338b}{TIM\_DIER\_CC4IE}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6ad0f562a014572793b49fe87184338b}{TIM\_DIER\_CC4IE}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{04723\ \}}
\DoxyCodeLine{04724\ }
\DoxyCodeLine{04731\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_EnableIT\_COM(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04732\ \{}
\DoxyCodeLine{04733\ \ \ SET\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gade8a374e04740aac1ece248b868522fe}{TIM\_DIER\_COMIE}});}
\DoxyCodeLine{04734\ \}}
\DoxyCodeLine{04735\ }
\DoxyCodeLine{04742\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_DisableIT\_COM(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04743\ \{}
\DoxyCodeLine{04744\ \ \ CLEAR\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gade8a374e04740aac1ece248b868522fe}{TIM\_DIER\_COMIE}});}
\DoxyCodeLine{04745\ \}}
\DoxyCodeLine{04746\ }
\DoxyCodeLine{04753\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IsEnabledIT\_COM(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04754\ \{}
\DoxyCodeLine{04755\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gade8a374e04740aac1ece248b868522fe}{TIM\_DIER\_COMIE}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gade8a374e04740aac1ece248b868522fe}{TIM\_DIER\_COMIE}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{04756\ \}}
\DoxyCodeLine{04757\ }
\DoxyCodeLine{04764\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_EnableIT\_TRIG(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04765\ \{}
\DoxyCodeLine{04766\ \ \ SET\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa755fef2c4e96c63f2ea1cd9a32f956a}{TIM\_DIER\_TIE}});}
\DoxyCodeLine{04767\ \}}
\DoxyCodeLine{04768\ }
\DoxyCodeLine{04775\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_DisableIT\_TRIG(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04776\ \{}
\DoxyCodeLine{04777\ \ \ CLEAR\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa755fef2c4e96c63f2ea1cd9a32f956a}{TIM\_DIER\_TIE}});}
\DoxyCodeLine{04778\ \}}
\DoxyCodeLine{04779\ }
\DoxyCodeLine{04786\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IsEnabledIT\_TRIG(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04787\ \{}
\DoxyCodeLine{04788\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa755fef2c4e96c63f2ea1cd9a32f956a}{TIM\_DIER\_TIE}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa755fef2c4e96c63f2ea1cd9a32f956a}{TIM\_DIER\_TIE}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{04789\ \}}
\DoxyCodeLine{04790\ }
\DoxyCodeLine{04797\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_EnableIT\_BRK(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04798\ \{}
\DoxyCodeLine{04799\ \ \ SET\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga1fcb0d6d9fb7486a5901032fd81aef6a}{TIM\_DIER\_BIE}});}
\DoxyCodeLine{04800\ \}}
\DoxyCodeLine{04801\ }
\DoxyCodeLine{04808\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_DisableIT\_BRK(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04809\ \{}
\DoxyCodeLine{04810\ \ \ CLEAR\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga1fcb0d6d9fb7486a5901032fd81aef6a}{TIM\_DIER\_BIE}});}
\DoxyCodeLine{04811\ \}}
\DoxyCodeLine{04812\ }
\DoxyCodeLine{04819\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IsEnabledIT\_BRK(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04820\ \{}
\DoxyCodeLine{04821\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga1fcb0d6d9fb7486a5901032fd81aef6a}{TIM\_DIER\_BIE}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga1fcb0d6d9fb7486a5901032fd81aef6a}{TIM\_DIER\_BIE}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{04822\ \}}
\DoxyCodeLine{04823\ }
\DoxyCodeLine{04827\ }
\DoxyCodeLine{04837\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_EnableDMAReq\_UPDATE(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04838\ \{}
\DoxyCodeLine{04839\ \ \ SET\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gab9f47792b1c2f123464a2955f445c811}{TIM\_DIER\_UDE}});}
\DoxyCodeLine{04840\ \}}
\DoxyCodeLine{04841\ }
\DoxyCodeLine{04848\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_DisableDMAReq\_UPDATE(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04849\ \{}
\DoxyCodeLine{04850\ \ \ CLEAR\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gab9f47792b1c2f123464a2955f445c811}{TIM\_DIER\_UDE}});}
\DoxyCodeLine{04851\ \}}
\DoxyCodeLine{04852\ }
\DoxyCodeLine{04859\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IsEnabledDMAReq\_UPDATE(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04860\ \{}
\DoxyCodeLine{04861\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gab9f47792b1c2f123464a2955f445c811}{TIM\_DIER\_UDE}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gab9f47792b1c2f123464a2955f445c811}{TIM\_DIER\_UDE}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{04862\ \}}
\DoxyCodeLine{04863\ }
\DoxyCodeLine{04870\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_EnableDMAReq\_CC1(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04871\ \{}
\DoxyCodeLine{04872\ \ \ SET\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gae181bb16ec916aba8ba86f58f745fdfd}{TIM\_DIER\_CC1DE}});}
\DoxyCodeLine{04873\ \}}
\DoxyCodeLine{04874\ }
\DoxyCodeLine{04881\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_DisableDMAReq\_CC1(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04882\ \{}
\DoxyCodeLine{04883\ \ \ CLEAR\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gae181bb16ec916aba8ba86f58f745fdfd}{TIM\_DIER\_CC1DE}});}
\DoxyCodeLine{04884\ \}}
\DoxyCodeLine{04885\ }
\DoxyCodeLine{04892\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IsEnabledDMAReq\_CC1(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04893\ \{}
\DoxyCodeLine{04894\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gae181bb16ec916aba8ba86f58f745fdfd}{TIM\_DIER\_CC1DE}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gae181bb16ec916aba8ba86f58f745fdfd}{TIM\_DIER\_CC1DE}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{04895\ \}}
\DoxyCodeLine{04896\ }
\DoxyCodeLine{04903\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_EnableDMAReq\_CC2(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04904\ \{}
\DoxyCodeLine{04905\ \ \ SET\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga58f97064991095b28c91028ca3cca28e}{TIM\_DIER\_CC2DE}});}
\DoxyCodeLine{04906\ \}}
\DoxyCodeLine{04907\ }
\DoxyCodeLine{04914\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_DisableDMAReq\_CC2(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04915\ \{}
\DoxyCodeLine{04916\ \ \ CLEAR\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga58f97064991095b28c91028ca3cca28e}{TIM\_DIER\_CC2DE}});}
\DoxyCodeLine{04917\ \}}
\DoxyCodeLine{04918\ }
\DoxyCodeLine{04925\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IsEnabledDMAReq\_CC2(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04926\ \{}
\DoxyCodeLine{04927\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga58f97064991095b28c91028ca3cca28e}{TIM\_DIER\_CC2DE}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga58f97064991095b28c91028ca3cca28e}{TIM\_DIER\_CC2DE}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{04928\ \}}
\DoxyCodeLine{04929\ }
\DoxyCodeLine{04936\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_EnableDMAReq\_CC3(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04937\ \{}
\DoxyCodeLine{04938\ \ \ SET\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga1567bff5dc0564b26a8b3cff1f0fe0a4}{TIM\_DIER\_CC3DE}});}
\DoxyCodeLine{04939\ \}}
\DoxyCodeLine{04940\ }
\DoxyCodeLine{04947\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_DisableDMAReq\_CC3(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04948\ \{}
\DoxyCodeLine{04949\ \ \ CLEAR\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga1567bff5dc0564b26a8b3cff1f0fe0a4}{TIM\_DIER\_CC3DE}});}
\DoxyCodeLine{04950\ \}}
\DoxyCodeLine{04951\ }
\DoxyCodeLine{04958\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IsEnabledDMAReq\_CC3(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04959\ \{}
\DoxyCodeLine{04960\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga1567bff5dc0564b26a8b3cff1f0fe0a4}{TIM\_DIER\_CC3DE}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga1567bff5dc0564b26a8b3cff1f0fe0a4}{TIM\_DIER\_CC3DE}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{04961\ \}}
\DoxyCodeLine{04962\ }
\DoxyCodeLine{04969\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_EnableDMAReq\_CC4(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04970\ \{}
\DoxyCodeLine{04971\ \ \ SET\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaaba034412c54fa07024e516492748614}{TIM\_DIER\_CC4DE}});}
\DoxyCodeLine{04972\ \}}
\DoxyCodeLine{04973\ }
\DoxyCodeLine{04980\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_DisableDMAReq\_CC4(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04981\ \{}
\DoxyCodeLine{04982\ \ \ CLEAR\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaaba034412c54fa07024e516492748614}{TIM\_DIER\_CC4DE}});}
\DoxyCodeLine{04983\ \}}
\DoxyCodeLine{04984\ }
\DoxyCodeLine{04991\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IsEnabledDMAReq\_CC4(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{04992\ \{}
\DoxyCodeLine{04993\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaaba034412c54fa07024e516492748614}{TIM\_DIER\_CC4DE}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaaba034412c54fa07024e516492748614}{TIM\_DIER\_CC4DE}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{04994\ \}}
\DoxyCodeLine{04995\ }
\DoxyCodeLine{05002\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_EnableDMAReq\_COM(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{05003\ \{}
\DoxyCodeLine{05004\ \ \ SET\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga79c3fab9d33de953a0a7f7d6516c73bc}{TIM\_DIER\_COMDE}});}
\DoxyCodeLine{05005\ \}}
\DoxyCodeLine{05006\ }
\DoxyCodeLine{05013\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_DisableDMAReq\_COM(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{05014\ \{}
\DoxyCodeLine{05015\ \ \ CLEAR\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga79c3fab9d33de953a0a7f7d6516c73bc}{TIM\_DIER\_COMDE}});}
\DoxyCodeLine{05016\ \}}
\DoxyCodeLine{05017\ }
\DoxyCodeLine{05024\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IsEnabledDMAReq\_COM(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{05025\ \{}
\DoxyCodeLine{05026\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga79c3fab9d33de953a0a7f7d6516c73bc}{TIM\_DIER\_COMDE}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga79c3fab9d33de953a0a7f7d6516c73bc}{TIM\_DIER\_COMDE}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{05027\ \}}
\DoxyCodeLine{05028\ }
\DoxyCodeLine{05035\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_EnableDMAReq\_TRIG(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{05036\ \{}
\DoxyCodeLine{05037\ \ \ SET\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga5a752d4295f100708df9b8be5a7f439d}{TIM\_DIER\_TDE}});}
\DoxyCodeLine{05038\ \}}
\DoxyCodeLine{05039\ }
\DoxyCodeLine{05046\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_DisableDMAReq\_TRIG(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{05047\ \{}
\DoxyCodeLine{05048\ \ \ CLEAR\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga5a752d4295f100708df9b8be5a7f439d}{TIM\_DIER\_TDE}});}
\DoxyCodeLine{05049\ \}}
\DoxyCodeLine{05050\ }
\DoxyCodeLine{05057\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_TIM\_IsEnabledDMAReq\_TRIG(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{05058\ \{}
\DoxyCodeLine{05059\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga5a752d4295f100708df9b8be5a7f439d}{TIM\_DIER\_TDE}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga5a752d4295f100708df9b8be5a7f439d}{TIM\_DIER\_TDE}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{05060\ \}}
\DoxyCodeLine{05061\ }
\DoxyCodeLine{05065\ }
\DoxyCodeLine{05075\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_GenerateEvent\_UPDATE(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{05076\ \{}
\DoxyCodeLine{05077\ \ \ SET\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a04248d87f48303fd2267810104a7878d}{EGR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga16f52a8e9aad153223405b965566ae91}{TIM\_EGR\_UG}});}
\DoxyCodeLine{05078\ \}}
\DoxyCodeLine{05079\ }
\DoxyCodeLine{05086\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_GenerateEvent\_CC1(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{05087\ \{}
\DoxyCodeLine{05088\ \ \ SET\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a04248d87f48303fd2267810104a7878d}{EGR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga0a1318609761df5de5213e9e75b5aa6a}{TIM\_EGR\_CC1G}});}
\DoxyCodeLine{05089\ \}}
\DoxyCodeLine{05090\ }
\DoxyCodeLine{05097\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_GenerateEvent\_CC2(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{05098\ \{}
\DoxyCodeLine{05099\ \ \ SET\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a04248d87f48303fd2267810104a7878d}{EGR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga5423de00e86aeb8a4657a509af485055}{TIM\_EGR\_CC2G}});}
\DoxyCodeLine{05100\ \}}
\DoxyCodeLine{05101\ }
\DoxyCodeLine{05108\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_GenerateEvent\_CC3(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{05109\ \{}
\DoxyCodeLine{05110\ \ \ SET\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a04248d87f48303fd2267810104a7878d}{EGR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga064d2030abccc099ded418fd81d6aa07}{TIM\_EGR\_CC3G}});}
\DoxyCodeLine{05111\ \}}
\DoxyCodeLine{05112\ }
\DoxyCodeLine{05119\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_GenerateEvent\_CC4(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{05120\ \{}
\DoxyCodeLine{05121\ \ \ SET\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a04248d87f48303fd2267810104a7878d}{EGR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga1c4e5555dd3be8ab1e631d1053f4a305}{TIM\_EGR\_CC4G}});}
\DoxyCodeLine{05122\ \}}
\DoxyCodeLine{05123\ }
\DoxyCodeLine{05130\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_GenerateEvent\_COM(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{05131\ \{}
\DoxyCodeLine{05132\ \ \ SET\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a04248d87f48303fd2267810104a7878d}{EGR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gadb06f8bb364307695c7d6a028391de7b}{TIM\_EGR\_COMG}});}
\DoxyCodeLine{05133\ \}}
\DoxyCodeLine{05134\ }
\DoxyCodeLine{05141\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_GenerateEvent\_TRIG(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{05142\ \{}
\DoxyCodeLine{05143\ \ \ SET\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a04248d87f48303fd2267810104a7878d}{EGR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga2eabface433d6adaa2dee3df49852585}{TIM\_EGR\_TG}});}
\DoxyCodeLine{05144\ \}}
\DoxyCodeLine{05145\ }
\DoxyCodeLine{05152\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_GenerateEvent\_BRK(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{05153\ \{}
\DoxyCodeLine{05154\ \ \ SET\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a04248d87f48303fd2267810104a7878d}{EGR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga08c5635a0ac0ce5618485319a4fa0f18}{TIM\_EGR\_BG}});}
\DoxyCodeLine{05155\ \}}
\DoxyCodeLine{05156\ }
\DoxyCodeLine{05163\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_TIM\_GenerateEvent\_BRK2(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx)}
\DoxyCodeLine{05164\ \{}
\DoxyCodeLine{05165\ \ \ SET\_BIT(TIMx-\/>\mbox{\hyperlink{struct_t_i_m___type_def_a04248d87f48303fd2267810104a7878d}{EGR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga42a7335ccbf7565d45b3efd51c213af2}{TIM\_EGR\_B2G}});}
\DoxyCodeLine{05166\ \}}
\DoxyCodeLine{05167\ }
\DoxyCodeLine{05171\ }
\DoxyCodeLine{05172\ \textcolor{preprocessor}{\#if\ defined(USE\_FULL\_LL\_DRIVER)}\textcolor{preprocessor}{}}
\DoxyCodeLine{05176\ }
\DoxyCodeLine{05177\ ErrorStatus\ LL\_TIM\_DeInit(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx);}
\DoxyCodeLine{05178\ \textcolor{keywordtype}{void}\ LL\_TIM\_StructInit(LL\_TIM\_InitTypeDef\ *TIM\_InitStruct);}
\DoxyCodeLine{05179\ ErrorStatus\ LL\_TIM\_Init(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ \textcolor{keyword}{const}\ LL\_TIM\_InitTypeDef\ *TIM\_InitStruct);}
\DoxyCodeLine{05180\ \textcolor{keywordtype}{void}\ LL\_TIM\_OC\_StructInit(LL\_TIM\_OC\_InitTypeDef\ *TIM\_OC\_InitStruct);}
\DoxyCodeLine{05181\ ErrorStatus\ LL\_TIM\_OC\_Init(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ Channel,\ \textcolor{keyword}{const}\ LL\_TIM\_OC\_InitTypeDef\ *TIM\_OC\_InitStruct);}
\DoxyCodeLine{05182\ \textcolor{keywordtype}{void}\ LL\_TIM\_IC\_StructInit(LL\_TIM\_IC\_InitTypeDef\ *TIM\_ICInitStruct);}
\DoxyCodeLine{05183\ ErrorStatus\ LL\_TIM\_IC\_Init(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ uint32\_t\ Channel,\ \textcolor{keyword}{const}\ LL\_TIM\_IC\_InitTypeDef\ *TIM\_IC\_InitStruct);}
\DoxyCodeLine{05184\ \textcolor{keywordtype}{void}\ LL\_TIM\_ENCODER\_StructInit(LL\_TIM\_ENCODER\_InitTypeDef\ *TIM\_EncoderInitStruct);}
\DoxyCodeLine{05185\ ErrorStatus\ LL\_TIM\_ENCODER\_Init(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ \textcolor{keyword}{const}\ LL\_TIM\_ENCODER\_InitTypeDef\ *TIM\_EncoderInitStruct);}
\DoxyCodeLine{05186\ \textcolor{keywordtype}{void}\ LL\_TIM\_HALLSENSOR\_StructInit(LL\_TIM\_HALLSENSOR\_InitTypeDef\ *TIM\_HallSensorInitStruct);}
\DoxyCodeLine{05187\ ErrorStatus\ LL\_TIM\_HALLSENSOR\_Init(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ \textcolor{keyword}{const}\ LL\_TIM\_HALLSENSOR\_InitTypeDef\ *TIM\_HallSensorInitStruct);}
\DoxyCodeLine{05188\ \textcolor{keywordtype}{void}\ LL\_TIM\_BDTR\_StructInit(LL\_TIM\_BDTR\_InitTypeDef\ *TIM\_BDTRInitStruct);}
\DoxyCodeLine{05189\ ErrorStatus\ LL\_TIM\_BDTR\_Init(\mbox{\hyperlink{struct_t_i_m___type_def}{TIM\_TypeDef}}\ *TIMx,\ \textcolor{keyword}{const}\ LL\_TIM\_BDTR\_InitTypeDef\ *TIM\_BDTRInitStruct);}
\DoxyCodeLine{05193\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ USE\_FULL\_LL\_DRIVER\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{05194\ }
\DoxyCodeLine{05198\ }
\DoxyCodeLine{05202\ }
\DoxyCodeLine{05203\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ TIM1\ ||\ TIM2\ ||\ TIM3\ ||\ TIM4\ ||\ TIM5\ ||\ TIM6\ ||\ TIM7\ ||\ TIM8\ ||\ TIM12\ ||\ TIM13\ ||TIM14\ ||\ TIM15\ ||\ TIM16\ ||\ TIM17\ \ ||\ TIM23\ \ ||\ TIM24\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{05204\ }
\DoxyCodeLine{05208\ }
\DoxyCodeLine{05209\ \textcolor{preprocessor}{\#ifdef\ \_\_cplusplus}}
\DoxyCodeLine{05210\ \}}
\DoxyCodeLine{05211\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{05212\ }
\DoxyCodeLine{05213\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ \_\_STM32H7xx\_LL\_TIM\_H\ */}\textcolor{preprocessor}{}}

\end{DoxyCode}
